DS90LV027ATMX from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Positive power supply pin, 3.3 V ± 0.3 V; recommended supply range is 3 V to 3.6 V.
2	DI 1	input	TTL/CMOS driver input for channel 1; VIH is 2 V minimum and VIL is 0.8 V maximum, with input voltage absolute maximum of 3.6 V.
3	DI 2	input	TTL/CMOS driver input for channel 2; VIH is 2 V minimum and VIL is 0.8 V maximum, with input voltage absolute maximum of 3.6 V.
4	GND	power_in	Ground pin for the device.
5	DO- 2	output	Inverting LVDS driver output for channel 2; output differential voltage is 250 to 450 mV into a 100 Ω load, and short-circuit current is -5.7 to -8 mA.
6	DO+ 2	output	Noninverting LVDS driver output for channel 2; output differential voltage is 250 to 450 mV into a 100 Ω load, and short-circuit current is -5.7 to -8 mA.
7	DO+ 1	output	Noninverting LVDS driver output for channel 1; output differential voltage is 250 to 450 mV into a 100 Ω load, and short-circuit current is -5.7 to -8 mA.
8	DO- 1	output	Inverting LVDS driver output for channel 1; output differential voltage is 250 to 450 mV into a 100 Ω load, and short-circuit current is -5.7 to -8 mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Logic ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.3		4	V		4
Input voltage, DI	VIN	-0.3		3.6	V		4
Output voltage, DO±	VO	-0.3		3.9	V		4
Maximum package power dissipation at 25°C, D package				1190	mW	at 25°C	4
Lead temperature range, soldering				260	°C	4 s	4
Storage temperature	Tstg	-65		150	°C		4
Human-body model (HBM) ESD	V(ESD)	-8000		8000	V	per ANSI/ESDA/JEDEC JS-001	4
Charged-device model (CDM) ESD	V(ESD)	-1000		1000	V	per JEDEC JESD22-C101	4
EIAJ ESD	V(ESD)	-1000		1000	V	0 Ω, 200 pF	4
IEC direct ESD	V(ESD)	-4000		4000	V	330 Ω, 150 pF	4
Supply voltage	VCC	3	3.3	3.6	V		4
Operating free-air temperature	TA	-40	25	85	°C		4
Junction-to-ambient thermal resistance, low-K	RθJA		212		°C/W	Low-K thermal resistance	4
Junction-to-ambient thermal resistance, high-K	RθJA		112		°C/W	High-K thermal resistance	4
Junction-to-case (top) thermal resistance	RθJC(top)		69.1		°C/W		4
Junction-to-board thermal resistance	RθJB		47.7		°C/W		4
Junction-to-top characterization parameter	ψJT		15.2		°C/W		4
Junction-to-board characterization parameter	ψJB		47.2		°C/W		4
Differential output voltage	VOD	250	360	450	mV	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
VOD magnitude change	ΔVOD		1	35	mV	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
Output high voltage	VOH	1.4		1.6	V	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
Output low voltage	VOL	0.9		1.1	V	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
Offset voltage	VOS	1.125	1.2	1.375	V	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
Offset magnitude change	ΔVOS	0	3	25	mV	RL = 100 Ω (see Figure 15), DO+, DO− pins	5
Power-off leakage	IOXD	-10	1	10	μA	VOUT = VCC or GND, VCC = 0 V, DO+, DO− pins	5
Output short-circuit current	IOSD	-5.7		-8	mA	DO+, DO− pins	5
Input high voltage	VIH	2			V	DI pin	5
Input low voltage	VIL			0.8	V	DI pin	5
Input high current	IIH	-10	2	10	μA	VIN = 3.3 V or 2.4 V, DI pin	5
Input low current	IIL	-10	1	10	μA	VIN = GND or 0.5 V, DI pin	5
Input clamp voltage	VCL	-1.5		-0.6	V	ICL = −18 mA, DI pin	5
Power supply current, no load	ICC		8	14	mA	VIN = VCC or GND, VCC pin, No load	5
Power supply current, RL = 100 Ω	ICC		14	20	mA	VIN = VCC or GND, VCC pin, RL = 100 Ω	5
Differential propagation delay high to low	tPHLD	0.3	0.8	1.5	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Differential propagation delay low to high	tPLHD	0.3	1.1	1.5	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Differential pulse skew /tPHLD − tPLHD/	tSKD1	0	0.3	0.7	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Channel to channel skew	tSKD2	0	0.4	0.8	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Differential part to part skew	tSKD3	0		1	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Differential part to part skew	tSKD4	0		1.2	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Transition low to high time	tTLH	0.2	0.5	1	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Transition high to low time	tTHL	0.2	0.5	1	ns	RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)	5
Maximum operating frequency	fMAX	350			MHz	Output criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels switching	5

CAD (KiCad official)

Symbol: DS90LV027ATMX
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ds90lv027atmx-etched.step / ds90lv027atmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90lv027atmx.step / ds90lv027atmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (24 pp, sha256 daaaf013a321cbbd, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS90LV027ATMX

Verified DS90LV027ATMX

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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