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DS90LV004TVS

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Texas Instruments LVDS ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS90LV004TVS

Texas Instruments · LVDS ICs · TQFP-48(7x7)

DS90LV004TVS from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PEM0 input Pre-emphasis control input bit 0; use with PEM1 to select pre-emphasis level (off/low/medium/high).
2 PEM1 input Pre-emphasis control input bit 1; use with PEM0 to select pre-emphasis level (off/low/medium/high).
3 VDD power_in Supply voltage input, 3.3V nominal ±5%.
4 VDD power_in Supply voltage input, 3.3V nominal ±5%.
5 VDD power_in Supply voltage input, 3.3V nominal ±5%.
6 N/C unconnected No Connect.
7 VDD power_in Supply voltage input, 3.3V nominal ±5%.
8 GND power_in Ground reference for LVDS and CMOS circuitry.
9 GND power_in Ground reference for LVDS and CMOS circuitry.
10 VDD power_in Supply voltage input, 3.3V nominal ±5%.
11 VDD power_in Supply voltage input, 3.3V nominal ±5%.
12 PWDN input Power down enable input (active low); tri-states outputs in power down mode.
13 IN0+ input Channel 0 non-inverting LVDS differential input, 100-2400mV differential voltage range.
14 IN0− input Channel 0 inverting LVDS differential input, 100-2400mV differential voltage range.
15 IN1+ input Channel 1 non-inverting LVDS differential input, 100-2400mV differential voltage range.
16 IN1− input Channel 1 inverting LVDS differential input, 100-2400mV differential voltage range.
17 GND power_in Ground reference for LVDS and CMOS circuitry.
18 GND power_in Ground reference for LVDS and CMOS circuitry.
19 IN2+ input Channel 2 non-inverting LVDS differential input, 100-2400mV differential voltage range.
20 IN2− input Channel 2 inverting LVDS differential input, 100-2400mV differential voltage range.
21 IN3+ input Channel 3 non-inverting LVDS differential input, 100-2400mV differential voltage range.
22 IN3− input Channel 3 inverting LVDS differential input, 100-2400mV differential voltage range.
23 GND power_in Ground reference for LVDS and CMOS circuitry.
24 GND power_in Ground reference for LVDS and CMOS circuitry.
25 GND power_in Ground reference for LVDS and CMOS circuitry.
26 GND power_in Ground reference for LVDS and CMOS circuitry.
27 VDD power_in Supply voltage input, 3.3V nominal ±5%.
28 VDD power_in Supply voltage input, 3.3V nominal ±5%.
29 VDD power_in Supply voltage input, 3.3V nominal ±5%.
30 N/C unconnected No Connect.
31 N/C unconnected No Connect.
32 VDD power_in Supply voltage input, 3.3V nominal ±5%.
33 VDD power_in Supply voltage input, 3.3V nominal ±5%.
34 VDD power_in Supply voltage input, 3.3V nominal ±5%.
35 N/C unconnected No Connect.
36 N/C unconnected No Connect.
37 GND power_in Ground reference for LVDS and CMOS circuitry.
38 GND power_in Ground reference for LVDS and CMOS circuitry.
39 OUT3- output Channel 3 inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
40 OUT3+ output Channel 3 non-inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
41 OUT2− output Channel 2 inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
42 OUT2+ output Channel 2 non-inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
43 GND power_in Ground reference for LVDS and CMOS circuitry.
44 GND power_in Ground reference for LVDS and CMOS circuitry.
45 OUT1− output Channel 1 inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
46 OUT1+ output Channel 1 non-inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
47 OUT0− output Channel 0 inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.
48 OUT0+ output Channel 0 non-inverting LVDS differential output, 250-600mV differential voltage at 0% pre-emphasis.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: DS90LV004TVS
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90lv004tvs-etched.step / ds90lv004tvs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90lv004tvs.step / ds90lv004tvs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 e905d8b12ec26e9b, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF