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DS90CP02SP
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Texas Instruments Signal Switches, Multiplexers, Decoders, WQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# DS90CP02SP++**Texas Instruments** · Signal Switches, Multiplexers, Decoders · WQFN-28-EP(5x5)++DS90CP02SP from Texas Instruments, in a WQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 2 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 3 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 4 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 5 | SEL1 | input | LVTTL select control input that, with SEL0, sets which input each output is connected to. |+| 6 | SEL0 | input | LVTTL select control input that, with SEL1, sets which input each output is connected to. |+| 7 | EN0 | input | LVTTL output enable input (active low) for channel 0; EN0 and EN1 high together put both channels in power down. |+| 8 | N/C | unconnected | Not connected. |+| 9 | IN0+ | input | Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |+| 10 | IN0- | input | Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |+| 11 | VDD | power_in | Supply pin (labelled VDDA in the connection diagram), VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 12 | IN1+ | input | Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |+| 13 | IN1- | input | Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |+| 14 | VDD | power_in | Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 15 | EN1 | input | LVTTL output enable input (active low) for channel 1; EN0 and EN1 high together put both channels in power down. |+| 16 | VDD | power_in | Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 17 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 18 | VDD | power_in | Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 19 | VDD | power_in | Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 20 | N/C | unconnected | Not connected. |+| 21 | GND | power_in | Ground reference to LVDS and CMOS circuitry. |+| 22 | VDD | power_in | Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 23 | OUT1- | output | LVDS differential output that can be connected to either IN0± or IN1±. |+| 24 | OUT1+ | output | LVDS differential output that can be connected to either IN0± or IN1±. |+| 25 | VDD | power_in | Supply pin (labelled VDDA in the connection diagram), VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane. |+| 26 | OUT0- | output | LVDS differential output that can be connected to either IN0± or IN1±. |+| 27 | OUT0+ | output | LVDS differential output that can be connected to either IN0± or IN1±. |+| 28 | N/C | unconnected | Not connected. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-28-EP(5x5) |+| Category | Logic |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `DS90CP02SP`+- Footprint: `Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm`+- 3D model: WQFN-28-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `ds90cp02sp-etched.step` / `ds90cp02sp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90cp02sp.step` / `ds90cp02sp.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90cp02) (15 pp, sha256 `8d0a8913954c18b3`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90cp02sp-datasheet.pdf)
page.jsonadded+328@@ -0,0 +1,328 @@+{+ "slug": "ds90cp02sp",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Signal Switches, Multiplexers, Decoders, WQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "ds90cp02sp",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds90cp02sp.kicad_sym",+ "ds90cp02sp.kicad_mod",+ "ds90cp02sp.glb",+ "ds90cp02sp.step",+ "ds90cp02sp.lbr",+ "docs/hero.png",+ "docs/ds90cp02sp-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds90cp02sp-hero.glb",+ "ds90cp02sp-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS90CP02SP",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-28-EP(5x5)",+ "pin_count": 29,+ "category": "Logic",+ "subcategory": "Signal Switches, Multiplexers, Decoders",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds90cp02",+ "parts": {+ "symbol": "ds90cp02sp.kicad_sym",+ "footprint": "ds90cp02sp.kicad_mod",+ "model_3d": "ds90cp02sp-hero.glb",+ "model_3d_plain": "ds90cp02sp.glb",+ "model_3d_step": "ds90cp02sp-etched.step",+ "model_3d_step_plain": "ds90cp02sp.step",+ "lbr": "ds90cp02sp.lbr"+ },+ "distributor_links": {+ "lcsc": "C2674601",+ "digikey": "2156-DS90CP02SP-ND"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:05:13Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-DS90CP02SP-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "5",+ "name": "SEL1",+ "type": "input",+ "description": "LVTTL select control input that, with SEL0, sets which input each output is connected to."+ },+ {+ "number": "6",+ "name": "SEL0",+ "type": "input",+ "description": "LVTTL select control input that, with SEL1, sets which input each output is connected to."+ },+ {+ "number": "7",+ "name": "EN0",+ "type": "input",+ "description": "LVTTL output enable input (active low) for channel 0; EN0 and EN1 high together put both channels in power down."+ },+ {+ "number": "8",+ "name": "N/C",+ "type": "unconnected",+ "description": "Not connected."+ },+ {+ "number": "9",+ "name": "IN0+",+ "type": "input",+ "description": "Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible."+ },+ {+ "number": "10",+ "name": "IN0-",+ "type": "input",+ "description": "Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible."+ },+ {+ "number": "11",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin (labelled VDDA in the connection diagram), VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "12",+ "name": "IN1+",+ "type": "input",+ "description": "Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible."+ },+ {+ "number": "13",+ "name": "IN1-",+ "type": "input",+ "description": "Differential input, LVDS, Bus LVDS, CML, or LVPECL compatible."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "15",+ "name": "EN1",+ "type": "input",+ "description": "LVTTL output enable input (active low) for channel 1; EN0 and EN1 high together put both channels in power down."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "17",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "18",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "19",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "20",+ "name": "N/C",+ "type": "unconnected",+ "description": "Not connected."+ },+ {+ "number": "21",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference to LVDS and CMOS circuitry."+ },+ {+ "number": "22",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin, VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "23",+ "name": "OUT1-",+ "type": "output",+ "description": "LVDS differential output that can be connected to either IN0± or IN1±."+ },+ {+ "number": "24",+ "name": "OUT1+",+ "type": "output",+ "description": "LVDS differential output that can be connected to either IN0± or IN1±."+ },+ {+ "number": "25",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin (labelled VDDA in the connection diagram), VDD = 3.3V ±0.3V, with at least 4 low ESR 0.01 µF bypass capacitors from VDD to the GND plane."+ },+ {+ "number": "26",+ "name": "OUT0-",+ "type": "output",+ "description": "LVDS differential output that can be connected to either IN0± or IN1±."+ },+ {+ "number": "27",+ "name": "OUT0+",+ "type": "output",+ "description": "LVDS differential output that can be connected to either IN0± or IN1±."+ },+ {+ "number": "28",+ "name": "N/C",+ "type": "unconnected",+ "description": "Not connected."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet describes the package as UQFN-28 (NJD0028A), not WQFN-28-EP(5x5). The pin count and DA; Pins 11 and 25 are labelled VDDA in the connection diagram, but Table 1 lists them under VDD. I used; The exposed pad is printed as 'DAP', not a number. I used 'DAP' as its pin number.",+ "exposed pad 29 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 15,+ "cost_usd": 0.2621,+ "at": "2026-10-08T16:04:54"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90cp02",+ "pages": 15,+ "sha256": "8d0a8913954c18b3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds90cp02sp.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e9d6d740f505b03e5aa0ac826330f9e269344b84656d051f50eb07ac162749eb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds90cp02sp-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4475095abf5c3b0d437ed22d433171812438674860ef2154dba1a6ef8e70aac1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}