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DS90C387AVJD

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Texas Instruments LVDS ICs, TQFP-100(14x14). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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DS90C387AVJD

Texas Instruments · LVDS ICs · TQFP-100(14x14)

DS90C387AVJD from Texas Instruments, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G11 input TTL-level green pixel bit 11 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
2 G10 input TTL-level green pixel bit 10 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
3 R17 input TTL-level red pixel bit 17 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
4 R16 input TTL-level red pixel bit 16 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
5 R15 input TTL-level red pixel bit 15 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
6 R14 input TTL-level red pixel bit 14 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
7 R13 input TTL-level red pixel bit 13 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
8 R12 input TTL-level red pixel bit 12 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
9 R11 input TTL-level red pixel bit 11 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
10 R10 input TTL-level red pixel bit 10 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
11 CLKIN input TTL-level pixel clock input; 32.5-112 MHz in dual-pixel mode; transition time 1.0-3.0 ns; 5V-tolerant.
12 PLLVCC power_in 3.0-3.6 V supply for PLL circuitry; decouple independently from digital VCC.
13 GND power_in Ground for TTL input buffers and digital logic circuitry.
14 PRE input Pre-emphasis level select; open/1 MΩ pull-up = 0.75 V standard LVDS, 100 Ω pull-up = Vcc for 100% pre-emphasis; do not tie to GND.
15 PLLSEL input PLL range select; must be tied to VCC for auto-range; GND or NC reserved; typical shift point 55-68 MHz.
16 PLLGND power_in Ground for PLL circuitry; decouple independently from digital GND.
17 PLLGND power_in Ground for PLL circuitry; decouple independently from digital GND.
18 PLLGND power_in Ground for PLL circuitry; decouple independently from digital GND.
19 PLLVCC power_in 3.0-3.6 V supply for PLL circuitry; decouple independently from digital VCC.
20 R_FB input Data strobe edge select; high = rising edge, low = falling edge strobe; 5V-tolerant; internal pull-down.
21 R_FDE input DE polarity strobe select; high = data active when DE is high; 5V-tolerant; internal pull-down.
22 PD input Active-low power-down; asserts TRI-STATE on all LVDS outputs and shuts down PLL; ICCT Z max 50 µA; drive high after VCC stable.
23 DUAL input Pixel mode select; low = 24-bit single pixel (A4-A7 and CLK2 disabled), high = 48-bit dual pixel, 1/2 VCC = single-in/dual-out.
24 GND power_in Ground for TTL input buffers and digital logic circuitry.
25 LVDSGND power_in Ground for LVDS output drivers.
26 CLK2P/NC output Additional positive LVDS differential clock output, identical to CLK1P; leave unconnected (no pull-down) if not used.
27 CLK2M/NC output Additional negative LVDS differential clock output, identical to CLK1M; leave unconnected (no pull-down) if not used.
28 A7P output Positive LVDS differential data output, channel 7; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
29 A7M output Negative LVDS differential data output, channel 7; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
30 LVDSVCC power_in 3.0-3.6 V supply for LVDS output drivers.
31 A6P output Positive LVDS differential data output, channel 6; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
32 A6M output Negative LVDS differential data output, channel 6; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
33 A5P output Positive LVDS differential data output, channel 5; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
34 A5M output Negative LVDS differential data output, channel 5; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
35 LVDSGND power_in Ground for LVDS output drivers.
36 A4P output Positive LVDS differential data output, channel 4; VOD = 250-450 mV into 100 Ω; disabled in single-pixel mode (DUAL=low).
37 A4M output Negative LVDS differential data output, channel 4; VOD = 250-450 mV into 100 Ω; disabled in single-pixel mode (DUAL=low).
38 A3P output Positive LVDS differential data output, channel 3; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
39 A3M output Negative LVDS differential data output, channel 3; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
40 LVDSVCC power_in 3.0-3.6 V supply for LVDS output drivers.
41 CLK1P output Positive LVDS differential clock output 1; active in all pixel modes; VOD = 250-450 mV into 100 Ω.
42 CLK1M output Negative LVDS differential clock output 1; active in all pixel modes; VOD = 250-450 mV into 100 Ω.
43 LVDSGND power_in Ground for LVDS output drivers.
44 A2P output Positive LVDS differential data output, channel 2; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
45 A2M output Negative LVDS differential data output, channel 2; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
46 A1P output Positive LVDS differential data output, channel 1; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
47 A1M output Negative LVDS differential data output, channel 1; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
48 LVDSVCC power_in 3.0-3.6 V supply for LVDS output drivers.
49 A0P output Positive LVDS differential data output, channel 0; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
50 A0M output Negative LVDS differential data output, channel 0; VOD = 250-450 mV into 100 Ω; TRI-STATE during power-down.
51 LVDSGND power_in Ground for LVDS output drivers.
52 VCC power_in 3.0-3.6 V supply for TTL input buffers and digital circuitry; 100 mVp-p max supply noise.
53 GND power_in Ground for TTL input buffers and digital logic circuitry.
54 HSYNC input TTL-level horizontal sync control input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
55 VSYNC input TTL-level vertical sync control input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
56 DE input TTL-level data enable control input; active polarity set by R_FDE; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant.
57 B27 input TTL-level blue pixel bit 27 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
58 B26 input TTL-level blue pixel bit 26 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
59 B25 input TTL-level blue pixel bit 25 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
60 B24 input TTL-level blue pixel bit 24 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
61 B23 input TTL-level blue pixel bit 23 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
62 B22 input TTL-level blue pixel bit 22 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
63 B21 input TTL-level blue pixel bit 21 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
64 B20 input TTL-level blue pixel bit 20 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
65 G27 input TTL-level green pixel bit 27 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
66 VCC power_in 3.0-3.6 V supply for TTL input buffers and digital circuitry; 100 mVp-p max supply noise.
67 G26 input TTL-level green pixel bit 26 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
68 GND power_in Ground for TTL input buffers and digital logic circuitry.
69 G25 input TTL-level green pixel bit 25 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
70 G24 input TTL-level green pixel bit 24 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
71 G23 input TTL-level green pixel bit 23 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
72 G22 input TTL-level green pixel bit 22 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
73 G21 input TTL-level green pixel bit 21 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
74 G20 input TTL-level green pixel bit 20 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
75 R27 input TTL-level red pixel bit 27 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
76 R26 input TTL-level red pixel bit 26 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
77 R25 input TTL-level red pixel bit 25 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
78 R24 input TTL-level red pixel bit 24 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
79 R23 input TTL-level red pixel bit 23 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
80 R22 input TTL-level red pixel bit 22 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
81 R21 input TTL-level red pixel bit 21 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
82 VCC power_in 3.0-3.6 V supply for TTL input buffers and digital circuitry; 100 mVp-p max supply noise.
83 GND power_in Ground for TTL input buffers and digital logic circuitry.
84 R20 input TTL-level red pixel bit 20 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
85 B17 input TTL-level blue pixel bit 17 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
86 B16 input TTL-level blue pixel bit 16 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
87 B15 input TTL-level blue pixel bit 15 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
88 B14 input TTL-level blue pixel bit 14 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
89 B13 input TTL-level blue pixel bit 13 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
90 B12 input TTL-level blue pixel bit 12 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
91 B11 input TTL-level blue pixel bit 11 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
92 B10 input TTL-level blue pixel bit 10 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
93 G17 input TTL-level green pixel bit 17 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
94 G16 input TTL-level green pixel bit 16 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
95 G15 input TTL-level green pixel bit 15 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
96 G14 input TTL-level green pixel bit 14 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
97 VCC power_in 3.0-3.6 V supply for TTL input buffers and digital circuitry; 100 mVp-p max supply noise.
98 GND power_in Ground for TTL input buffers and digital logic circuitry.
99 G13 input TTL-level green pixel bit 13 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.
100 G12 input TTL-level green pixel bit 12 data input; VIH min 2.0 V, VIL max 0.8 V; 5V-tolerant; internal pull-down holds low when undriven.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-100(14x14)
Category Interface
Pins 100

CAD (KiCad official)

  • Symbol: DS90C387AVJD
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: ds90c387avjd-etched.step / ds90c387avjd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c387avjd.step / ds90c387avjd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 0e78a29ef17eef1d, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF