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DS90C241IVSX

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Texas Instruments Serializers, Deserializers, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS90C241IVSX

Texas Instruments · Serializers, Deserializers · TQFP-48(7x7)

DS90C241IVSX from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN[20] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
2 DIN[21] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
3 DIN[22] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
4 DIN[23] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
5 DCAOFF input LVCMOS reserved input; this pin must be tied LOW.
6 VSSL power_in Digital ground for Tx logic.
7 VDDL power_in Digital voltage supply (VDD) for Tx logic power.
8 DCBOFF input LVCMOS reserved input; this pin must be tied LOW.
9 TPWDNB input LVCMOS transmitter power-down bar; H = transmitter enabled, L = power down (sleep) with DOUT± in TRI-STATE and PLL shut down.
10 TCLK input LVCMOS transmitter parallel interface clock input; strobe edge set by the TRFB pin.
11 TRFB input LVCMOS transmitter clock edge select; H = data strobed on rising clock edge, L = falling clock edge.
12 VODSEL input LVCMOS VOD level select; L = approximately ±400 mV (RL = 100 Ω, normal use), H = approximately ±750 mV for long cables.
13 RESRVD input LVCMOS reserved input; this pin must be tied LOW.
14 VDDPT1 power_in Analog voltage supply (VDD) for PLL power.
15 VSSPT1 power_in Analog ground for PLL.
16 VDDPT0 power_in Analog voltage supply (VDD) for VCO power.
17 VSSPT0 power_in Analog ground for VCO.
18 DEN input LVCMOS transmitter data enable; H = LVDS driver outputs enabled, L = DOUT± in TRI-STATE with PLL still operational and locked to TCLK.
19 DOUT- output LVDS transmitter inverted (-) output, intended to be loaded with 100 Ω to DOUT+ and AC-coupled with a 100-nF capacitor.
20 DOUT+ output LVDS transmitter true (+) output, intended to be loaded with 100 Ω to DOUT- and AC-coupled with a 100-nF capacitor.
21 VSSDR power_in Analog ground for LVDS output.
22 VDDDR power_in Analog voltage supply (VDD) for LVDS output power.
23 PRE input Pre-emphasis level select; NC = pre-emphasis off, tie to VSS through external RPRE (recommended ≥ 3 kΩ) to set the level.
24 VSS power_in ESD ground.
25 DIN[0] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
26 DIN[1] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
27 DIN[2] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
28 DIN[3] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
29 DIN[4] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
30 VDDT power_in Digital voltage supply (VDD) for Tx serializer power.
31 VSST power_in Digital ground for Tx serializer.
32 DIN[5] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
33 DIN[6] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
34 DIN[7] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
35 DIN[8] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
36 DIN[9] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
37 DIN[10] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
38 DIN[11] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
39 DIN[12] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
40 DIN[13] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
41 DIN[14] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
42 VDDIT power_in Digital voltage supply (VDD) for Tx input power.
43 VSSIT power_in Digital ground for Tx input.
44 DIN[15] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
45 DIN[16] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
46 DIN[17] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
47 DIN[18] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.
48 DIN[19] input LVCMOS transmitter parallel interface data input; tie LOW if unused, do not float.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: DS90C241IVSX
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90c241ivsx-etched.step / ds90c241ivsx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c241ivsx.step / ds90c241ivsx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 b59137d02c6a2297, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF