component

DS90C189TWRTDTQ1

Public Made by Adom

by adom

Texas Instruments Serializers / Deserializers, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ds90c189twrtdtq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DS90C189TWRTDTQ1

Texas Instruments · Serializers / Deserializers · VQFN-64-EP(9x9)

DS90C189TWRTDTQ1 from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_9 input 1.8-V LVCMOS video data input from the IN_[13:9] group; includes pull-down.
2 IN_10 input 1.8-V LVCMOS video data input from the IN_[13:9] group; includes pull-down.
3 IN_11 input 1.8-V LVCMOS video data input from the IN_[13:9] group; includes pull-down.
4 IN_12 input 1.8-V LVCMOS video data input from the IN_[13:9] group; includes pull-down.
5 IN_13 input 1.8-V LVCMOS video data input from the IN_[13:9] group; includes pull-down.
6 IN_CLK input 1.8-V LVCMOS pixel input clock; includes pull-down.
7 IN_14 input 1.8-V LVCMOS video data input from the IN_[17:14] group; includes pull-down.
8 IN_15 input 1.8-V LVCMOS video data input from the IN_[17:14] group; includes pull-down.
9 IN_16 input 1.8-V LVCMOS video data input from the IN_[17:14] group; includes pull-down.
10 IN_17 input 1.8-V LVCMOS video data input from the IN_[17:14] group; includes pull-down.
11 RSVD input Reserved pin; tie to ground.
12 HS/VS/DE input 1.8-V LVCMOS video control signal input (HS = horizontal sync, VS = vertical sync, DE = data enable); the per-pin assignment is not stated.
13 HS/VS/DE input 1.8-V LVCMOS video control signal input (HS = horizontal sync, VS = vertical sync, DE = data enable); the per-pin assignment is not stated.
14 NC unconnected No connect pin; leave open.
15 NC unconnected No connect pin; leave open.
16 VDDP power_in PLL power supply pin, 1.8 V.
17 NC unconnected No connect pin; leave open.
18 HS/VS/DE input 1.8-V LVCMOS video control signal input (HS = horizontal sync, VS = vertical sync, DE = data enable); the per-pin assignment is not stated.
19 IN_21 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
20 IN_22 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
21 IN_23 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
22 IN_24 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
23 IN_25 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
24 IN_26 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
25 IN_27 input 1.8-V LVCMOS video data input from the IN_[27:21] group; includes pull-down.
26 RFB input Rising/falling clock edge select input: 0 = falling edge, 1 = rising edge; includes pull-down.
27 MODE0 input Mode control input: 0 = single in / single out, 1 = single in / dual out; includes pull-down.
28 VDD power_in Core power supply pin, 1.8 V.
29 NC unconnected No connect pin; leave open.
30 OB_3+ output Channel B LVDS output data (true); expects 100 Ω termination.
31 VDDTX power_in Power supply for LVDS drivers, 1.8 V.
32 OB_3- output Channel B LVDS output data (complement); expects 100 Ω termination.
33 OB_C+ output Channel B LVDS output clock (true); expects 100 Ω termination.
34 OB_C- output Channel B LVDS output clock (complement); expects 100 Ω termination.
35 OB_2+ output Channel B LVDS output data (true); expects 100 Ω termination.
36 OB_2- output Channel B LVDS output data (complement); expects 100 Ω termination.
37 OB_1+ output Channel B LVDS output data (true); expects 100 Ω termination.
38 OB_1- output Channel B LVDS output data (complement); expects 100 Ω termination.
39 OB_0+ output Channel B LVDS output data (true); expects 100 Ω termination.
40 OB_0- output Channel B LVDS output data (complement); expects 100 Ω termination.
41 OA_3+ output Channel A LVDS output data (true); expects 100 Ω termination.
42 OA_3- output Channel A LVDS output data (complement); expects 100 Ω termination.
43 OA_C+ output Channel A LVDS output clock (true); expects 100 Ω termination.
44 OA_C- output Channel A LVDS output clock (complement); expects 100 Ω termination.
45 OA_2- output Channel A LVDS output data (complement); expects 100 Ω termination.
46 OA_2+ output Channel A LVDS output data (true); expects 100 Ω termination.
47 OA_1- output Channel A LVDS output data (complement); expects 100 Ω termination.
48 OA_1+ output Channel A LVDS output data (true); expects 100 Ω termination.
49 OA_0- output Channel A LVDS output data (complement); expects 100 Ω termination.
50 OA_0+ output Channel A LVDS output data (true); expects 100 Ω termination.
51 NC unconnected No connect pin; leave open.
52 PDB input Power-down (sleep) control input: 0 = sleep (power-down mode), 1 = device active; includes pull-down.
53 IN_0 input 1.8-V LVCMOS video data input (general-purpose or L/R control bit); includes pull-down.
54 VODSEL input LVDS VOD level select input: 0 = low swing, 1 = normal swing; includes pull-down.
55 IN_1 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
56 IN_2 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
57 IN_3 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
58 IN_4 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
59 IN_5 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
60 IN_6 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
61 IN_7 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
62 IN_8 input 1.8-V LVCMOS video data input from the IN_[8:1] group; includes pull-down.
63 NC unconnected No connect pin; leave open.
64 VDD power_in Core power supply pin, 1.8 V.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

CAD (KiCad official)

  • Symbol: DS90C189TWRTDTQ1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ds90c189twrtdtq1-etched.step / ds90c189twrtdtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c189twrtdtq1.step / ds90c189twrtdtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 9e4e2584fca427c9, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF