component
DS90C124IVS
Public Made by Adomby adom
Texas Instruments LVDS ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+84@@ -0,0 +1,84 @@+# DS90C124IVS++**Texas Instruments** · LVDS ICs · TQFP-48(7x7)++DS90C124IVS from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RPWDNB | input | Receiver power-down bar: H enables the receiver; L puts it in power-down (sleep) with ROUT[23:0], RCLK and LOCK in TRI-STATE and the PLL shut down. |+| 2 | RESRVD | input | Reserved pin that must be tied LOW. |+| 3 | ROUT[23] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 4 | ROUT[22] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 5 | ROUT[21] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 6 | ROUT[20] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 7 | VDDOR3 | power_in | Digital LVCMOS output supply for ROUT Group 3 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 8 | VSSOR3 | power_in | Digital ground for the LVCMOS output driver of ROUT Group 3. |+| 9 | ROUT[19] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 10 | ROUT[18] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 11 | ROUT[17] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 12 | ROUT[16] | output | LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down. |+| 13 | ROUT[15] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 14 | ROUT[14] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 15 | ROUT[13] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 16 | ROUT[12] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 17 | LOCK | output | Receiver PLL status flag: H means the PLL is locked; L means unlocked, and ROUT[23:0] and RCLK are TRI-STATED. |+| 18 | RCLK | output | LVCMOS parallel interface clock output; the strobe edge is set by RRFB and the output is TRI-STATE when REN is L. |+| 19 | VSSOR2 | power_in | Digital ground for the LVCMOS output driver of ROUT Group 2 and RCLK. |+| 20 | VDDOR2 | power_in | Digital LVCMOS output supply for ROUT Group 2 and RCLK (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 21 | ROUT[11] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 22 | ROUT[10] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 23 | ROUT[9] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 24 | ROUT[8] | output | LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down. |+| 25 | ROUT[4] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 26 | ROUT[5] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 27 | ROUT[6] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 28 | ROUT[7] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 29 | VSSOR1 | power_in | Digital ground for the LVCMOS output driver of ROUT Group 1. |+| 30 | VDDOR1 | power_in | Digital LVCMOS output supply for ROUT Group 1 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 31 | ROUT[0] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 32 | ROUT[1] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 33 | ROUT[2] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 34 | ROUT[3] | output | LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down. |+| 35 | VSSR0 | power_in | Digital logic ground for the receiver core. |+| 36 | VDDR0 | power_in | Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 37 | VDDR1 | power_in | Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 38 | VSSR1 | power_in | Digital logic ground for the receiver core. |+| 39 | VDDIR | power_in | Analog supply for the LVDS receiver inputs (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 40 | VSSIR | power_in | Analog ground for the LVDS receiver inputs. |+| 41 | RIN+ | input | LVDS receiver true (+) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor. |+| 42 | RIN- | input | LVDS receiver inverted (-) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor. |+| 43 | RRFB | input | Receiver clock edge select: H strobes ROUT and RCLK on the rising edge, L strobes them on the falling edge. |+| 44 | VSSPR1 | power_in | Analog ground for the PLL VCO. |+| 45 | VDDPR1 | power_in | Analog supply for the PLL VCO (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 46 | VSSPR0 | power_in | Analog ground for the receiver PLL. |+| 47 | VDDPR0 | power_in | Analog supply for the receiver PLL (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range). |+| 48 | REN | input | Receiver data enable: H enables ROUT[23:0] and RCLK; L TRI-STATEs them while the PLL stays locked to TCLK. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `DS90C124IVS`+- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`+- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `ds90c124ivs-etched.step` / `ds90c124ivs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90c124ivs.step` / `ds90c124ivs.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90c124) (43 pp, sha256 `b59137d02c6a2297`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90c124ivs-datasheet.pdf)
page.jsonadded+437@@ -0,0 +1,437 @@+{+ "slug": "ds90c124ivs",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments LVDS ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "ds90c124ivs",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds90c124ivs.kicad_sym",+ "ds90c124ivs.kicad_mod",+ "ds90c124ivs.glb",+ "ds90c124ivs.step",+ "ds90c124ivs.lbr",+ "docs/hero.png",+ "docs/ds90c124ivs-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds90c124ivs-hero.glb",+ "ds90c124ivs-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS90C124IVS",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "LVDS ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds90c124",+ "parts": {+ "symbol": "ds90c124ivs.kicad_sym",+ "footprint": "ds90c124ivs.kicad_mod",+ "model_3d": "ds90c124ivs-hero.glb",+ "model_3d_plain": "ds90c124ivs.glb",+ "model_3d_step": "ds90c124ivs-etched.step",+ "model_3d_step_plain": "ds90c124ivs.step",+ "lbr": "ds90c124ivs.lbr"+ },+ "distributor_links": {+ "lcsc": "C1522513"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:17:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RPWDNB",+ "type": "input",+ "description": "Receiver power-down bar: H enables the receiver; L puts it in power-down (sleep) with ROUT[23:0], RCLK and LOCK in TRI-STATE and the PLL shut down."+ },+ {+ "number": "2",+ "name": "RESRVD",+ "type": "input",+ "description": "Reserved pin that must be tied LOW."+ },+ {+ "number": "3",+ "name": "ROUT[23]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "4",+ "name": "ROUT[22]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "5",+ "name": "ROUT[21]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "6",+ "name": "ROUT[20]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "7",+ "name": "VDDOR3",+ "type": "power_in",+ "description": "Digital LVCMOS output supply for ROUT Group 3 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "8",+ "name": "VSSOR3",+ "type": "power_in",+ "description": "Digital ground for the LVCMOS output driver of ROUT Group 3."+ },+ {+ "number": "9",+ "name": "ROUT[19]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "10",+ "name": "ROUT[18]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "11",+ "name": "ROUT[17]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "12",+ "name": "ROUT[16]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "13",+ "name": "ROUT[15]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "14",+ "name": "ROUT[14]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "15",+ "name": "ROUT[13]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "16",+ "name": "ROUT[12]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "17",+ "name": "LOCK",+ "type": "output",+ "description": "Receiver PLL status flag: H means the PLL is locked; L means unlocked, and ROUT[23:0] and RCLK are TRI-STATED."+ },+ {+ "number": "18",+ "name": "RCLK",+ "type": "output",+ "description": "LVCMOS parallel interface clock output; the strobe edge is set by RRFB and the output is TRI-STATE when REN is L."+ },+ {+ "number": "19",+ "name": "VSSOR2",+ "type": "power_in",+ "description": "Digital ground for the LVCMOS output driver of ROUT Group 2 and RCLK."+ },+ {+ "number": "20",+ "name": "VDDOR2",+ "type": "power_in",+ "description": "Digital LVCMOS output supply for ROUT Group 2 and RCLK (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "21",+ "name": "ROUT[11]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "22",+ "name": "ROUT[10]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "23",+ "name": "ROUT[9]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "24",+ "name": "ROUT[8]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "25",+ "name": "ROUT[4]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "26",+ "name": "ROUT[5]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "27",+ "name": "ROUT[6]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "28",+ "name": "ROUT[7]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "29",+ "name": "VSSOR1",+ "type": "power_in",+ "description": "Digital ground for the LVCMOS output driver of ROUT Group 1."+ },+ {+ "number": "30",+ "name": "VDDOR1",+ "type": "power_in",+ "description": "Digital LVCMOS output supply for ROUT Group 1 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "31",+ "name": "ROUT[0]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "32",+ "name": "ROUT[1]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "33",+ "name": "ROUT[2]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "34",+ "name": "ROUT[3]",+ "type": "output",+ "description": "LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down."+ },+ {+ "number": "35",+ "name": "VSSR0",+ "type": "power_in",+ "description": "Digital logic ground for the receiver core."+ },+ {+ "number": "36",+ "name": "VDDR0",+ "type": "power_in",+ "description": "Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "37",+ "name": "VDDR1",+ "type": "power_in",+ "description": "Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "38",+ "name": "VSSR1",+ "type": "power_in",+ "description": "Digital logic ground for the receiver core."+ },+ {+ "number": "39",+ "name": "VDDIR",+ "type": "power_in",+ "description": "Analog supply for the LVDS receiver inputs (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "40",+ "name": "VSSIR",+ "type": "power_in",+ "description": "Analog ground for the LVDS receiver inputs."+ },+ {+ "number": "41",+ "name": "RIN+",+ "type": "input",+ "description": "LVDS receiver true (+) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor."+ },+ {+ "number": "42",+ "name": "RIN-",+ "type": "input",+ "description": "LVDS receiver inverted (-) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor."+ },+ {+ "number": "43",+ "name": "RRFB",+ "type": "input",+ "description": "Receiver clock edge select: H strobes ROUT and RCLK on the rising edge, L strobes them on the falling edge."+ },+ {+ "number": "44",+ "name": "VSSPR1",+ "type": "power_in",+ "description": "Analog ground for the PLL VCO."+ },+ {+ "number": "45",+ "name": "VDDPR1",+ "type": "power_in",+ "description": "Analog supply for the PLL VCO (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "46",+ "name": "VSSPR0",+ "type": "power_in",+ "description": "Analog ground for the receiver PLL."+ },+ {+ "number": "47",+ "name": "VDDPR0",+ "type": "power_in",+ "description": "Analog supply for the receiver PLL (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range)."+ },+ {+ "number": "48",+ "name": "REN",+ "type": "input",+ "description": "Receiver data enable: H enables ROUT[23:0] and RCLK; L TRI-STATEs them while the PLL stays locked to TCLK."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet lists ROUT[7:0] only as the grouped pin ranges 25-28 and 31-34. The per-bit assignment; The datasheet covers both the DS90C241 serializer and the DS90C124 deserializer. The MPN DS90C124IVS; The datasheet gives no per-pin voltage limits. The 3.0 V to 3.6 V range on the supply pins is the de"+ ],+ "pages_sent": 17,+ "cost_usd": 0.133,+ "at": "2026-10-08T19:16:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90c124",+ "pages": 43,+ "sha256": "b59137d02c6a2297",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds90c124ivs.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "14ca7676e4932e92f0eca0c6d56ce3018cd28a2531204a70ab7bbacb3eeb3cf5",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds90c124ivs-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "200ebd58b2b379e28db1830347f1e3913b972640cc3a7544bf3df697018e3407",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}