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DS90C124IVS

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Texas Instruments LVDS ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS90C124IVS

Texas Instruments · LVDS ICs · TQFP-48(7x7)

DS90C124IVS from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RPWDNB input Receiver power-down bar: H enables the receiver; L puts it in power-down (sleep) with ROUT[23:0], RCLK and LOCK in TRI-STATE and the PLL shut down.
2 RESRVD input Reserved pin that must be tied LOW.
3 ROUT[23] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
4 ROUT[22] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
5 ROUT[21] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
6 ROUT[20] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
7 VDDOR3 power_in Digital LVCMOS output supply for ROUT Group 3 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
8 VSSOR3 power_in Digital ground for the LVCMOS output driver of ROUT Group 3.
9 ROUT[19] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
10 ROUT[18] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
11 ROUT[17] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
12 ROUT[16] output LVCMOS receiver parallel data output, Group 3; TRI-STATE when REN is L or the receiver is powered down.
13 ROUT[15] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
14 ROUT[14] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
15 ROUT[13] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
16 ROUT[12] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
17 LOCK output Receiver PLL status flag: H means the PLL is locked; L means unlocked, and ROUT[23:0] and RCLK are TRI-STATED.
18 RCLK output LVCMOS parallel interface clock output; the strobe edge is set by RRFB and the output is TRI-STATE when REN is L.
19 VSSOR2 power_in Digital ground for the LVCMOS output driver of ROUT Group 2 and RCLK.
20 VDDOR2 power_in Digital LVCMOS output supply for ROUT Group 2 and RCLK (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
21 ROUT[11] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
22 ROUT[10] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
23 ROUT[9] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
24 ROUT[8] output LVCMOS receiver parallel data output, Group 2; TRI-STATE when REN is L or the receiver is powered down.
25 ROUT[4] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
26 ROUT[5] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
27 ROUT[6] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
28 ROUT[7] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
29 VSSOR1 power_in Digital ground for the LVCMOS output driver of ROUT Group 1.
30 VDDOR1 power_in Digital LVCMOS output supply for ROUT Group 1 (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
31 ROUT[0] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
32 ROUT[1] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
33 ROUT[2] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
34 ROUT[3] output LVCMOS receiver parallel data output, Group 1; TRI-STATE when REN is L or the receiver is powered down.
35 VSSR0 power_in Digital logic ground for the receiver core.
36 VDDR0 power_in Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
37 VDDR1 power_in Digital logic supply for the receiver core (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
38 VSSR1 power_in Digital logic ground for the receiver core.
39 VDDIR power_in Analog supply for the LVDS receiver inputs (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
40 VSSIR power_in Analog ground for the LVDS receiver inputs.
41 RIN+ input LVDS receiver true (+) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor.
42 RIN- input LVDS receiver inverted (-) input, to be terminated with 100 Ω and AC-coupled with a 100-nF capacitor.
43 RRFB input Receiver clock edge select: H strobes ROUT and RCLK on the rising edge, L strobes them on the falling edge.
44 VSSPR1 power_in Analog ground for the PLL VCO.
45 VDDPR1 power_in Analog supply for the PLL VCO (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
46 VSSPR0 power_in Analog ground for the receiver PLL.
47 VDDPR0 power_in Analog supply for the receiver PLL (nominal 3.3 V, 3.0 V to 3.6 V recommended operating range).
48 REN input Receiver data enable: H enables ROUT[23:0] and RCLK; L TRI-STATEs them while the PLL stays locked to TCLK.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: DS90C124IVS
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90c124ivs-etched.step / ds90c124ivs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c124ivs.step / ds90c124ivs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 b59137d02c6a2297, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF