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DS90C032BTMX

Texas Instruments · LVDS ICs · SOIC-16

DS90C032BTMX from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN- input Inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
2 RIN+ input Non-inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
3 ROUT output Receiver CMOS/TTL-compatible output that is HIGH for VID ≥ +0.1 V or open/terminated failsafe inputs, LOW for VID ≤ −0.1 V, and high-impedance (TRI-STATE) when disabled.
4 EN input Active-high enable, OR-ed with EN*; VIH minimum 2.0 V and VIL maximum 0.8 V, and the outputs are TRI-STATE when EN is low and EN* is high.
5 ROUT output Receiver CMOS/TTL-compatible output that is HIGH for VID ≥ +0.1 V or open/terminated failsafe inputs, LOW for VID ≤ −0.1 V, and high-impedance (TRI-STATE) when disabled.
6 RIN+ input Non-inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
7 RIN- input Inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
8 GND power_in Ground pin for the device.
9 RIN- input Inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
10 RIN+ input Non-inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
11 ROUT output Receiver CMOS/TTL-compatible output that is HIGH for VID ≥ +0.1 V or open/terminated failsafe inputs, LOW for VID ≤ −0.1 V, and high-impedance (TRI-STATE) when disabled.
12 EN* input Active-low enable, OR-ed with EN; VIH minimum 2.0 V and VIL maximum 0.8 V, and the outputs are TRI-STATE when EN is low and EN* is high.
13 ROUT output Receiver CMOS/TTL-compatible output that is HIGH for VID ≥ +0.1 V or open/terminated failsafe inputs, LOW for VID ≤ −0.1 V, and high-impedance (TRI-STATE) when disabled.
14 RIN+ input Non-inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
15 RIN- input Inverting receiver input; each receiver input must stay within the specified 0 V to +2.4 V range measured from the pin to ground.
16 VCC power_in Power supply pin, +5 V ±10% (recommended supply range 4.5 V to 5.5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 4.5 5 5.5 V 2
Receiver Input Voltage 2.4 V 2
Operating Free Air Temperature TA -40 25 85 °C 2
Supply Voltage VCC -0.3 6 V 2
Input Voltage (RIN+, RIN−) -0.3 5.8 V 2
Enable Input Voltage (EN, EN*) -0.3 V max printed as (VCC + 0.3V) 2
Output Voltage (ROUT) -0.3 V max printed as (VCC + 0.3V) 2
Maximum Package Power Dissipation 1025 mW at +25°C 2
Storage Temperature Range -65 150 °C 2
Maximum Lead Temperature, Soldering 260 °C 4 seconds 2
Maximum Junction Temperature 150 °C 2
ESD Rating (HBM) 2 kV HBM, 1.5 kΩ, 100 pF 2
ESD Rating (EIAJ) 250 V EIAJ, 0 Ω, 200 pF 2
Differential Input High Threshold VTH 100 mV VCM = +1.2V 3
Differential Input Low Threshold VTL -100 mV VCM = +1.2V 3
Input Current IIN -10 1 10 μA VCC = 5.5V or 0V; VIN = +2.4V 3
Output High Voltage VOH 3.8 4.9 V IOH = −0.4 mA, VID = +200 mV 3
Output Low Voltage VOL 0.07 0.3 V IOL = 2 mA, VID = −200 mV 3
Output Short Circuit Current IOS -15 -60 -100 mA Enabled, VOUT = 0V 3
Output TRI-STATE Current IOZ -10 1 10 μA Disabled, VOUT = 0V or VCC 3
Input High Voltage VIH 2 V 3
Input Low Voltage VIL 0.8 V 3
Input Current (EN, EN*) II -10 1 10 μA 3
Input Clamp Voltage VCL -1.5 -0.8 V ICL = −18 mA 3
No Load Supply Current, Receivers Enabled ICC 3.5 10 mA EN, EN* = VCC or GND, Inputs Open 3
No Load Supply Current, Receivers Enabled ICC 3.7 11 mA EN, EN* = 2.4 or 0.5, Inputs Open 3
No Load Supply Current, Receivers Disabled ICCZ 3.5 10 mA EN = GND, EN* = VCC, Inputs Open 3
Differential Propagation Delay High to Low tPHLD 1.5 3.4 5 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Differential Propagation Delay Low to High tPLHD 1.5 3.48 5 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Differential Skew tSKD 0 80 600 ps VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Channel-to-Channel Skew tSK1 0 0.6 1 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Rise Time tTLH 0.5 2 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Fall Time tTHL 0.5 2 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 3
Disable Time High to Z tPHZ 10 15 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 3
Disable Time Low to Z tPLZ 10 15 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 3
Enable Time Z to High tPZH 4 10 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 3
Enable Time Z to Low tPZL 4 10 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 3
Differential Propagation Delay High to Low tPHLD 1 3.4 6 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Differential Propagation Delay Low to High tPLHD 1 3.48 6 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Differential Skew tSKD 0 0.08 1.2 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Channel-to-Channel Skew tSK1 0 0.6 1.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Chip to Chip Skew tSK2 5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C 4
Rise Time tTLH 0.5 2.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Fall Time tTHL 0.5 2.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 4
Disable Time High to Z tPHZ 10 20 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 4
Disable Time Low to Z tPLZ 10 20 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 4
Enable Time Z to High tPZH 4 15 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 4
Enable Time Z to Low tPZL 4 15 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 4

CAD (KiCad official)

  • Symbol: DS90C032BTMX
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ds90c032btmx-etched.step / ds90c032btmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c032btmx.step / ds90c032btmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 47df7111d05405e7, retrieved 2026-11-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF