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DS90C032BTM

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Texas Instruments Pre-ordered Chips, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified DS90C032BTM

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DS90C032BTM · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 17-page datasheet
  • ✓distributor: lcsc C1544100, digikey DS90C032BTM-ND, mouser 926-DS90C032BTM
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-blcc2n_u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ds90c032btm.kicad_sym✓ ds90c032btm.kicad_mod✓ ds90c032btm.step
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Ray Publish 0.1.0 1e1de7b 10d ago

DS90C032BTM

Texas Instruments · Pre-ordered Chips · SOIC-16

DS90C032BTM from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN− input Inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and unused receiver inputs must be left open rather than tied to ground or any other voltage.
2 RIN+ input Non-inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and the receiver detects signals as low as 100 mV over a ±1V common-mode range centered around +1.2V.
3 ROUT tri_state Receiver CMOS (TTL compatible) output that goes HIGH for both failsafe conditions and is in TRI-STATE when the receiver is disabled.
4 EN input Active high enable pin, OR-ed with EN*; the receiver is disabled (output Z) when EN is low and EN* is high.
5 ROUT tri_state Receiver CMOS (TTL compatible) output that goes HIGH for both failsafe conditions and is in TRI-STATE when the receiver is disabled.
6 RIN+ input Non-inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and the receiver detects signals as low as 100 mV over a ±1V common-mode range centered around +1.2V.
7 RIN− input Inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and unused receiver inputs must be left open rather than tied to ground or any other voltage.
8 GND power_in Ground pin for the device.
9 RIN− input Inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and unused receiver inputs must be left open rather than tied to ground or any other voltage.
10 RIN+ input Non-inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and the receiver detects signals as low as 100 mV over a ±1V common-mode range centered around +1.2V.
11 ROUT tri_state Receiver CMOS (TTL compatible) output that goes HIGH for both failsafe conditions and is in TRI-STATE when the receiver is disabled.
12 EN* input Active low enable pin, OR-ed with EN; the receiver is disabled (output Z) when EN* is high and EN is low.
13 ROUT tri_state Receiver CMOS (TTL compatible) output that goes HIGH for both failsafe conditions and is in TRI-STATE when the receiver is disabled.
14 RIN+ input Non-inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and the receiver detects signals as low as 100 mV over a ±1V common-mode range centered around +1.2V.
15 RIN− input Inverting receiver input pin; each LVDS input operates over 0V to +2.4V measured from each pin to ground, and unused receiver inputs must be left open rather than tied to ground or any other voltage.
16 VCC power_in Power supply pin, +5V ± 10% (recommended supply range +4.5 V to +5.5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Input High Threshold VTH 100 mV VCM = +1.2V 3
Differential Input Low Threshold VTL -100 mV 3
Input Current (RIN+/RIN-) IIN -10 1 10 μA VCC = 5.5V or 0V, VIN = +2.4V 3
Output High Voltage VOH 3.8 4.9 V IOH = −0.4 mA, VID = +200 mV 3
Output High Voltage (input terminated) VOH 3.8 4.9 V IOH = −0.4 mA, Input terminated 3
Output Low Voltage VOL 0.07 0.3 V IOL = 2 mA, VID = −200 mV 3
Output Short Circuit Current IOS -15 -60 -100 mA Enabled, VOUT = 0V 3
Output TRI-STATE Current IOZ -10 1 10 μA Disabled, VOUT = 0V or VCC 3
Input High Voltage (EN, EN*) VIH 2 V 3
Input Low Voltage (EN, EN*) VIL 0.8 V 3
Input Current (EN, EN*) II -10 1 10 μA 3
Input Clamp Voltage VCL -1.5 -0.8 V ICL = −18 mA 3
No Load Supply Current, Receivers Enabled ICC 3.5 10 mA EN, EN* = VCC or GND, Inputs Open 3
No Load Supply Current, Receivers Enabled ICC 3.7 11 mA EN, EN* = 2.4 or 0.5, Inputs Open 3
No Load Supply Current, Receivers Disabled ICCZ 3.5 10 mA EN = GND, EN* = VCC, Inputs Open 3
Differential Propagation Delay High to Low tPHLD 1.5 3.4 5 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Differential Propagation Delay Low to High tPLHD 1.5 3.48 5 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Differential Skew /tPHLD − tPLHD/ tSKD 0 80 600 ps VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Channel-to-Channel Skew tSK1 0 0.6 1 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Rise Time tTLH 0.5 2 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Fall Time tTHL 0.5 2 ns VCC = +5.0V, TA = +25°C; CL = 5 pF, VID = 200 mV 3
Disable Time High to Z tPHZ 10 15 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF 3
Disable Time Low to Z tPLZ 10 15 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF 3
Enable Time Z to High tPZH 4 10 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF 3
Enable Time Z to Low tPZL 4 10 ns VCC = +5.0V, TA = +25°C; RL = 2 kΩ, CL = 10 pF 3
Differential Propagation Delay High to Low tPHLD 1 3.4 6 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Differential Propagation Delay Low to High tPLHD 1 3.48 6 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Differential Skew /tPHLD − tPLHD/ tSKD 0 0.08 1.2 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Channel-to-Channel Skew tSK1 0 0.6 1.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Chip to Chip Skew tSK2 5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C 4
Rise Time tTLH 0.5 2.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Fall Time tTHL 0.5 2.5 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; CL = 5 pF, VID = 200 mV 4
Disable Time High to Z tPHZ 10 20 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF 4
Disable Time Low to Z tPLZ 10 20 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF 4
Enable Time Z to High tPZH 4 15 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF 4
Enable Time Z to Low tPZL 4 15 ns VCC = +5.0V ± 10%, TA = −40°C to +85°C; RL = 2 kΩ, CL = 10 pF 4
Supply Voltage (VCC) VCC 4.5 5 5.5 V 2
Receiver Input Voltage 2.4 V Minimum printed as GND 2
Operating Free Air Temperature TA -40 25 85 °C 2
Supply Voltage (VCC) VCC -0.3 6 V 2
Input Voltage (RIN+, RIN−) -0.3 5.8 V 2
Enable Input Voltage (EN, EN*) -0.3 V Maximum printed as (VCC + 0.3V) 2
Output Voltage (ROUT) -0.3 V Maximum printed as (VCC + 0.3V) 2
Maximum Package Power Dissipation 1025 mW at +25°C 2
Derate Power Dissipation 8.2 mW/°C above +25°C 2
Storage Temperature Range Tstg -65 150 °C 2
Maximum Lead Temperature, Soldering 260 °C 4 seconds 2
Maximum Junction Temperature TJ 150 °C 2
ESD HBM 2 kV HBM, 1.5 kΩ, 100 pF 2
ESD EIAJ 250 V EIAJ, 0 Ω, 200 pF 2

CAD (KiCad official)

  • Symbol: DS90C032BTM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ds90c032btm-etched.step / ds90c032btm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90c032btm.step / ds90c032btm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 b0972de640159839, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF