component
DS8575-33S3
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| ds8575-33s3-etched.glb | 17d ago |
| ds8575-33s3-etched.step | 17d ago |
| ds8575-33s3-hero.glb | 17d ago |
| ds8575-33s3-hero.overlay.json | 17d ago |
| ds8575-33s3.glb | 17d ago |
| ds8575-33s3.kicad_mod | 17d ago |
| ds8575-33s3.kicad_sym | 17d ago |
| ds8575-33s3.lbr | 17d ago |
| ds8575-33s3.step | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
DS8575-33S3
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3
DS8575-33S3 from DSTECH, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin of the regulator; input and output capacitor ground returns must connect back to this pin using as wide and short a trace as practical. |
| 2 | VOUT | power_out | Regulated output of the LDO; the output capacitor must be placed close to VOUT and GND and meet a minimum 1mΩ ESR with effective capacitance between 1µF and 22µF. |
| 3 | VIN | power_in | Supply input of the regulator, rated 1.2V to 5.5V, which requires a 1µF or larger input capacitor placed close to the VIN and GND pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT-23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 1.2 | 5.5 | V | 5 | ||
| DC Output Voltage Accuracy | -1 | 1 | % | ILOAD =0.1mA | 5 | ||
| Dropout Voltage (VOUT 3.3V uses VOUT ≥ 3V row) | VDROP_3V | 0.36 | 0.43 | V | VOUT ≥ 3V, ILOAD =300mA | 5 | |
| Ground Current | IQ | 0.25 | 0.45 | μA | ILOAD = 0mA | 5 | |
| Shutdown Ground Current | ISD | 0.01 | 0.1 | μA | VEN = 0V, VOUT = 0V | 5 | |
| Enable Threshold Voltage (EN rising) | VIH | 1 | V | EN Rising | 5 | ||
| Enable Threshold Voltage (EN falling) | VIL | 0.4 | V | EN Falling | 5 | ||
| EN Input Current | IEN | 10 | 100 | nA | VEN = 5V | 5 | |
| Line Regulation | ΔLINE | 0.8 | % | ILOAD =10mA, 2.5V ≤ VIN ≤ 5.5V or (VOUT + 0.2V) ≤ VIN ≤ 5.5V | 5 | ||
| Load Regulation | ΔLOAD | 0.8 | % | 10mA ≤ ILOAD ≤ 0.1A | 5 | ||
| Output Current Limit | ILIM | 301 | 550 | mA | VOUT = 0V | 5 | |
| Input Voltage (recommended) | VIN | 1.2 | 5.5 | V | 4 | ||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | °C | 4 | ||
| Ambient Temperature Range (recommended) | TA | -40 | 85 | °C | 4 | ||
| VIN to GND | VIN | -0.3 | 7 | V | 4 | ||
| VOUT, EN to GND | VOUT, EN | -0.3 | 6 | V | 4 | ||
| VOUT to VIN | VOUT-VIN | -6 | 0.3 | V | 4 | ||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 4 | |||
| Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature Range | TSTG | -60 | 150 | °C | 4 | ||
| ESD Susceptibility HBM | HBM | 2 | kV | HBM | 4 | ||
| Package Thermal Resistance SOT-23-3 | θJA | 220 | °C/W | TA=25°C, DSTECH EVB board (Note 2) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | must be back to the DS8575 ground pin using as wide and as short of a copper trace as is practical. | 10 |
CAD (KiCad official)
- Symbol:
DS8575-33S3 - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3 (KiCad packages3D, STEP)
- 3D model files:
ds8575-33s3-etched.step/ds8575-33s3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8575-33s3.step/ds8575-33s3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (16 pp, sha256
3628bb10c96c8f95, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).