component
DS8561-18S3
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS8561-18S3
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT23-3
DS8561-18S3 from DSTECH, in a SOT23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin of the regulator, to which the input and output capacitor grounds must return via short, wide traces. |
| 2 | VOUT | power_out | Regulated output port; the output capacitor should be 1uF to 22uF effective with ESR above 1mΩ, placed close to VOUT and GND, and the output stays stable across 0mA to 300mA load. |
| 3 | VIN | power_in | Power input port with an operating range of 1.2V to 5.5V (absolute maximum VIN to GND is -0.3V to 7V), decoupled with at least 1uF placed close to VIN and GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | 1.2 | 5.5 | V | 7 | ||
| Output voltage accuracy | -2 | 2 | % | ILOAD = 0.1mA | 7 | ||
| Current limit value | ILIM | 301 | 600 | mA | VOUT = 0V | 7 | |
| Shutdown current | ISD | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 | |
| EN input current | IEN | 10 | 100 | nA | VEN = 5V | 7 | |
| Input voltage (absolute maximum), VIN to GND | VIN | -0.3 | 7 | V | 6 | ||
| VOUT, EN to GND | VOUT, EN | -0.3 | 6 | V | 6 | ||
| VOUT to VIN | VOUT-VIN | -6 | 0.3 | V | 6 | ||
| Storage temperature range | -60 | 150 | °C | 6 | |||
| Junction temperature | 150 | °C | 6 | ||||
| Lead soldering temperature | 260 | °C | Soldering, 10 sec. | 6 | |||
| ESD HBM | 2 | KV | HBM | 6 | |||
| ESD MM | 200 | V | MM | 6 | |||
| ESD CDM | 2 | KV | CDM | 6 | |||
| Recommended input voltage | VIN | 1.2 | 5.5 | V | 6 | ||
| Application junction temperature range | -40 | 125 | °C | 6 | |||
| Application ambient temperature range | -40 | 85 | °C | 6 | |||
| Thermal resistance junction-to-ambient, SOT-23-3 | θJA | 200 | °C/W | TA = 25°C, DSTECH EVB board (Note 2) | 6 |
CAD (KiCad official)
- Symbol:
DS8561-18S3 - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT23-3 (KiCad packages3D, STEP)
- 3D model files:
ds8561-18s3-etched.step/ds8561-18s3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8561-18s3.step/ds8561-18s3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (19 pp, sha256
b28c6b5e18533c57, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).