component
DS8561-12SS3
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DS8561-12SS3
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23
DS8561-12SS3 from DSTECH, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the regulator; input and output capacitor grounds must return to this pin through short, wide traces. |
| 2 | VOUT | power_out | Output of the regulator, fixed at 1.2V for this variant; requires an output capacitor between 1µF and 22µF with minimum 1mΩ ESR, placed close to VOUT and GND. |
| 3 | VIN | power_in | Input supply voltage, 1.2V to 6V (absolute maximum VIN to GND is 7V); use a 1µF or larger input capacitor placed close to VIN and GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT-23 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 1.2 | 6 | V | 7 | ||
| DC Output Voltage Accuracy | -2 | 2 | % | ILOAD = 0.1mA | 7 | ||
| Shutdown Ground Current | ISD | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 | |
| Output Current Limit | ILIM | 301 | 600 | mA | VOUT = 0V | 7 | |
| Input Voltage | VIN | 1.2 | 6 | V | 6 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 6 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 6 | ||
| VIN to GND | VIN | -0.3 | 7 | V | 6 | ||
| VOUT, EN to GND | VOUT, EN | -0.3 | 6 | V | 6 | ||
| VOUT to VIN | VOUT-VIN | -6 | 0.3 | V | 6 | ||
| Junction Temperature | TJ | 150 | °C | 6 | |||
| Storage Temperature Range | TSTG | -60 | 150 | °C | 6 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec soldering | 6 | |||
| Package Thermal Resistance SSOT-23 | θJA | 250 | °C/W | TA=25°C, DSTECH EVB board (Note 2) | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | must be back to the DS8561 ground pin using as wide and as short of a copper trace as is practical. | 13 |
CAD (KiCad official)
- Symbol:
DS8561-12SS3 - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
ds8561-12ss3-etched.step/ds8561-12ss3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8561-12ss3.step/ds8561-12ss3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (19 pp, sha256
a28d0ffe805037d7, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DS8561-12SS3
**DSTECH** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23
DS8561-12SS3 from DSTECH, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the regulator; input and output capacitor grounds must return to this pin through short, wide traces. |
| 2 | VOUT | power_out | Output of the regulator, fixed at 1.2V for this variant; requires an output capacitor between 1µF and 22µF with minimum 1mΩ ESR, placed close to VOUT and GND. |
| 3 | VIN | power_in | Input supply voltage, 1.2V to 6V (absolute maximum VIN to GND is 7V); use a 1µF or larger input capacitor placed close to VIN and GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT-23 |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 1.2 | | 6 | V | | 7 |
| DC Output Voltage Accuracy | | -2 | | 2 | % | ILOAD = 0.1mA | 7 |
| Shutdown Ground Current | ISD | | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 |
| Output Current Limit | ILIM | 301 | 600 | | mA | VOUT = 0V | 7 |
| Input Voltage | VIN | 1.2 | | 6 | V | | 6 |
| Junction Temperature Range | TJ | -40 | | 125 | °C | | 6 |
| Ambient Temperature Range | TA | -40 | | 85 | °C | | 6 |
| VIN to GND | VIN | -0.3 | | 7 | V | | 6 |
| VOUT, EN to GND | VOUT, EN | -0.3 | | 6 | V | | 6 |
| VOUT to VIN | VOUT-VIN | -6 | | 0.3 | V | | 6 |
| Junction Temperature | TJ | | | 150 | °C | | 6 |
| Storage Temperature Range | TSTG | -60 | | 150 | °C | | 6 |
| Lead Temperature (Soldering) | | | | 260 | °C | 10 sec soldering | 6 |
| Package Thermal Resistance SSOT-23 | θJA | | 250 | | °C/W | TA=25°C, DSTECH EVB board (Note 2) | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | must be back to the DS8561 ground pin using as wide and as short of a copper trace as is practical. | 13 |
## CAD (KiCad official)
- Symbol: `DS8561-12SS3`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `ds8561-12ss3-etched.step` / `ds8561-12ss3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds8561-12ss3.step` / `ds8561-12ss3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [DSTECH datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603098710226456576) (19 pp, sha256 `a28d0ffe805037d7`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ds8561-12ss3-datasheet.pdf)