component
DS8561-12S3
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DS8561-12S3
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT23-3
DS8561-12S3 from DSTECH, in a SOT23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the datasheet's absolute maximum for VIN to GND is -0.3V to 7V and VOUT/EN to GND is -0.3V to 6V. |
| 2 | VOUT | power_out | Regulated voltage output (fixed 1.2V on this -12 variant); VOUT to GND is rated -0.3V to 6V and the datasheet recommends 1uF to 22uF effective output capacitance with ESR above 1mΩ. |
| 3 | VIN | power_in | Power input; recommended operating range is 1.2V to 5.5V, and a 1uF or larger input capacitor should be placed close to the VIN and GND pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.2 | 5.5 | V | 7 | ||
| Output voltage accuracy | -2 | 2 | % | ILOAD =0.1mA | 7 | ||
| Shutdown current | ISD | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 | |
| EN input current | IEN | 10 | 100 | nA | VEN = 5V | 7 | |
| Output current limit | ILIM | 301 | 600 | mA | VOUT = 0V | 7 | |
| Junction temperature (recommended operating) | -40 | 125 | °C | 6 | |||
| Ambient temperature (recommended operating) | -40 | 85 | °C | 6 | |||
| VIN to GND (absolute maximum) | -0.3 | 7 | V | Note 1 | 6 | ||
| VOUT, EN to GND (absolute maximum) | -0.3 | 6 | V | Note 1 | 6 | ||
| VOUT to VIN (absolute maximum) | -6 | 0.3 | V | Note 1 | 6 | ||
| Storage temperature range | -60 | 150 | °C | 6 | |||
| Junction temperature (absolute maximum) | 150 | °C | 6 | ||||
| Lead soldering temperature | 260 | °C | Soldering, 10 sec | 6 | |||
| ESD HBM | 2 | KV | HBM | 6 | |||
| ESD MM | 200 | V | MM | 6 | |||
| ESD CDM | 2 | KV | CDM | 6 | |||
| Dropout voltage (1.2V output) | VDROP_1.2V | 0.45 | V | ILOAD =300mA, VOUT = 1.2V | 7 | ||
| Quiescent current | IQ | 2 | μA | ILOAD = 0mA | 7 | ||
| EN threshold high | VIH | 1 | V | EN Rising | 7 | ||
| EN threshold low | VIL | 0.4 | V | EN Falling | 7 | ||
| Input voltage regulation | ΔLINE | 0.2 | % | ILOAD =30mA, 1.5V ≤ VIN ≤ 5.5V or (VOUT + 0.2V) ≤ VIN ≤ 5.5V | 7 | ||
| Load voltage regulation | ΔLOAD | 0.2 | % | 10mA ≤ ILOAD ≤ 0.3A | 7 | ||
| Power supply rejection ratio at 100Hz | PSRR | 80 | dB | ILOAD =5mA, VOUT =1.2V, VIN = 2V, f = 100Hz | 7 | ||
| Power supply rejection ratio at 1kHz | PSRR | 75 | dB | ILOAD =5mA, VOUT =1.2V, VIN = 2V, f = 1kHz | 7 | ||
| Output current noise | 80 | μVRMS | BW = 10Hz to 100kHz, COUT =1μF, VIN = 3.5V, ILOAD =0.1A, VOUT =1.2V | 7 | |||
| Over-temperature shutdown temperature | TSD | 155 | °C | ILOAD =10mA | 7 | ||
| Over-temperature shutdown hysteresis | ΔTSD | 15 | °C | 7 | |||
| Discharge resistance | RDC | 30 | Ω | EN = 0V, VOUT = 0.1V | 7 | ||
| Package thermal resistance junction-to-ambient, SOT-23-3 | θJA | 200 | °C/W | TA = 25°C, DSTECH EVB board (Note 2) | 6 |
CAD (KiCad official)
- Symbol:
DS8561-12S3 - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT23-3 (KiCad packages3D, STEP)
- 3D model files:
ds8561-12s3-etched.step/ds8561-12s3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8561-12s3.step/ds8561-12s3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (19 pp, sha256
b28c6b5e18533c57, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DS8561-12S3
**DSTECH** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT23-3
DS8561-12S3 from DSTECH, in a SOT23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the datasheet's absolute maximum for VIN to GND is -0.3V to 7V and VOUT/EN to GND is -0.3V to 6V. |
| 2 | VOUT | power_out | Regulated voltage output (fixed 1.2V on this -12 variant); VOUT to GND is rated -0.3V to 6V and the datasheet recommends 1uF to 22uF effective output capacitance with ESR above 1mΩ. |
| 3 | VIN | power_in | Power input; recommended operating range is 1.2V to 5.5V, and a 1uF or larger input capacitor should be placed close to the VIN and GND pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.2 | | 5.5 | V | | 7 |
| Output voltage accuracy | | -2 | | 2 | % | ILOAD =0.1mA | 7 |
| Shutdown current | ISD | | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 |
| EN input current | IEN | | 10 | 100 | nA | VEN = 5V | 7 |
| Output current limit | ILIM | 301 | 600 | | mA | VOUT = 0V | 7 |
| Junction temperature (recommended operating) | | -40 | | 125 | °C | | 6 |
| Ambient temperature (recommended operating) | | -40 | | 85 | °C | | 6 |
| VIN to GND (absolute maximum) | | -0.3 | | 7 | V | Note 1 | 6 |
| VOUT, EN to GND (absolute maximum) | | -0.3 | | 6 | V | Note 1 | 6 |
| VOUT to VIN (absolute maximum) | | -6 | | 0.3 | V | Note 1 | 6 |
| Storage temperature range | | -60 | | 150 | °C | | 6 |
| Junction temperature (absolute maximum) | | | | 150 | °C | | 6 |
| Lead soldering temperature | | | | 260 | °C | Soldering, 10 sec | 6 |
| ESD HBM | | | | 2 | KV | HBM | 6 |
| ESD MM | | | | 200 | V | MM | 6 |
| ESD CDM | | | | 2 | KV | CDM | 6 |
| Dropout voltage (1.2V output) | VDROP_1.2V | | 0.45 | | V | ILOAD =300mA, VOUT = 1.2V | 7 |
| Quiescent current | IQ | | 2 | | μA | ILOAD = 0mA | 7 |
| EN threshold high | VIH | | 1 | | V | EN Rising | 7 |
| EN threshold low | VIL | | 0.4 | | V | EN Falling | 7 |
| Input voltage regulation | ΔLINE | | 0.2 | | % | ILOAD =30mA, 1.5V ≤ VIN ≤ 5.5V or (VOUT + 0.2V) ≤ VIN ≤ 5.5V | 7 |
| Load voltage regulation | ΔLOAD | | 0.2 | | % | 10mA ≤ ILOAD ≤ 0.3A | 7 |
| Power supply rejection ratio at 100Hz | PSRR | | 80 | | dB | ILOAD =5mA, VOUT =1.2V, VIN = 2V, f = 100Hz | 7 |
| Power supply rejection ratio at 1kHz | PSRR | | 75 | | dB | ILOAD =5mA, VOUT =1.2V, VIN = 2V, f = 1kHz | 7 |
| Output current noise | | | 80 | | μVRMS | BW = 10Hz to 100kHz, COUT =1μF, VIN = 3.5V, ILOAD =0.1A, VOUT =1.2V | 7 |
| Over-temperature shutdown temperature | TSD | | 155 | | °C | ILOAD =10mA | 7 |
| Over-temperature shutdown hysteresis | ΔTSD | | 15 | | °C | | 7 |
| Discharge resistance | RDC | | 30 | | Ω | EN = 0V, VOUT = 0.1V | 7 |
| Package thermal resistance junction-to-ambient, SOT-23-3 | θJA | | 200 | | °C/W | TA = 25°C, DSTECH EVB board (Note 2) | 6 |
## CAD (KiCad official)
- Symbol: `DS8561-12S3`
- Footprint: `Package_TO_SOT_SMD:SOT-23-3`
- 3D model: SOT23-3 (KiCad packages3D, STEP)
- 3D model files: `ds8561-12s3-etched.step` / `ds8561-12s3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds8561-12s3.step` / `ds8561-12s3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [DSTECH datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905883642195968) (19 pp, sha256 `b28c6b5e18533c57`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ds8561-12s3-datasheet.pdf)