main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers ds8242-50s3: viewers · Ray 17d ago
ds8242-50s3-etched.glb Publish 0.1.0 · Ray 17d ago
ds8242-50s3-etched.step ds8242-50s3: factory component page (tier=lcsc) · Ray 17d ago
ds8242-50s3-hero.glb ds8242-50s3: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
ds8242-50s3-hero.overlay.json Publish 0.1.0 · Ray 17d ago
ds8242-50s3.glb Publish 0.1.0 · Ray 17d ago
ds8242-50s3.kicad_mod Publish 0.1.0 · Ray 17d ago
ds8242-50s3.kicad_sym Publish 0.1.0 · Ray 17d ago
ds8242-50s3.lbr Publish 0.1.0 · Ray 17d ago
ds8242-50s3.step Publish 0.1.0 · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago

DS8242-50S3

DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3

DS8242-50S3 from DSTECH, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference pin of the regulator; the input and output capacitors must return to this pin through as wide and short a copper trace as is practical.
2 VOUT power_out Regulated output of the LDO, 5.0V for this DS8242-50 variant; place the output capacitor (1µF to 22µF, minimum 1mΩ ESR) close to VOUT and GND.
3 VIN power_in Input supply pin rated 2V to 24V (absolute maximum VIN to GND is 30V); place a 1µF or larger input capacitor close to VIN and GND.

Key specifications

Parameter Value
Manufacturer DSTECH
Package SOT-23-3
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VIN 2 24 V 5
DC Output Voltage Accuracy -1 1 % ILOAD =0.1mA 5
Dropout Voltage VDROP 0.35 V ILOAD =100mA; VOUT ≥ 5V 5
Line Regulation ΔLINE 0.5 % ILOAD =1mA, 10V ≤ VIN ≤ 20V 5
Output Current Limit ILIM 501 700 mA VOUT =0 5
VIN to GND -0.3 30 V 4
VOUT to GND -0.3 6 V 4
VOUT to VIN -28 0.3 V 4
Junction Temperature 150 °C 4
Storage Temperature Range -40 150 °C 4
Lead Temperature (Soldering) 260 °C Soldering, 10 sec. 4
ESD Susceptibility HBM 2 KV 4
ESD Susceptibility MM 200 V 4
Input Voltage (recommended) VIN 2 24 V 4
Junction Temperature Range (recommended) -40 125 °C 4
Ambient Temperature Range (recommended) -40 85 °C 4
Package Thermal Resistance, SOT-23-3 θJA 200 °C/W TA=25°C, DSTECH EVB board (Note 2) 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper must be back to the DS8242 ground pin using as wide and as short of a copper trace as is practical. 8

CAD (KiCad official)

  • Symbol: DS8242-50S3
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3 (KiCad packages3D, STEP)
  • 3D model files: ds8242-50s3-etched.step / ds8242-50s3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds8242-50s3.step / ds8242-50s3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DSTECH datasheet (12 pp, sha256 02f10bfeea1c3ede, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF