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DS4424N+T&R

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Maxim Integrated Digital To Analog Converters (DACs), TDFN-14-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersds4424n+t&rfactory-2.0.0extractor-text

Verified DS4424N+T&R

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 15 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DS4424N+T&R · TDFN-14-EP(3x3) · 15 pins
  • ✓copper: 15 copper pads, none touching another net
  • ✓datasheet: all 15 pin names found in the 11-page datasheet
  • ✓distributor: lcsc C2682626, digikey 175-DS4424N+T&RTR-ND, mouser 700-DS4424NT&R
  • ✓family: DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-d578j2kt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 15 pins = 15 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 15 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ds4424n-t-r.kicad_sym✓ ds4424n-t-r.kicad_mod✓ ds4424n-t-r.step
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DS4424N+T&R

Maxim Integrated · Digital To Analog Converters (DACs) · TDFN-14-EP(3x3)

DS4424N+T&R from Maxim Integrated, in a TDFN-14-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDA bidirectional I2C serial data input/output; absolute maximum -0.5V to +6.0V relative to ground.
2 SCL input I2C serial clock input; absolute maximum -0.5V to +6.0V relative to ground, up to 400kHz.
3 GND power_in Ground.
4 FS3 passive Full-scale calibration input for OUT3; a 40kΩ to 160kΩ resistor to ground sets the full-scale current.
5 FS2 passive Full-scale calibration input for OUT2; a 40kΩ to 160kΩ resistor to ground sets the full-scale current.
6 FS1 passive Full-scale calibration input for OUT1; a 40kΩ to 160kΩ resistor to ground sets the full-scale current, with VRFS of 0.976V.
7 FS0 passive Full-scale calibration input for OUT0; a 40kΩ to 160kΩ resistor to ground sets the full-scale current, with VRFS of 0.976V.
8 OUT0 bidirectional Current output 0 that sinks or sources the current set by the I2C interface and the FS0 resistor, 50µA to 200µA full scale.
9 A0 input Address select input that sets the I2C slave address when connected to VCC or GND.
10 OUT1 bidirectional Current output 1 that sinks or sources the current set by the I2C interface and the FS1 resistor, 50µA to 200µA full scale.
11 A1 input Address select input that sets the I2C slave address when connected to VCC or GND.
12 OUT2 bidirectional Current output 2 that sinks or sources the current set by the I2C interface and the FS2 resistor, 50µA to 200µA full scale.
13 VCC power_in Power supply, 2.7V to 5.5V operating range.
14 OUT3 bidirectional Current output 3 that sinks or sources the current set by the I2C interface and the FS3 resistor, 50µA to 200µA full scale.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package TDFN-14-EP(3x3)
Category Data Converters
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 2.7 5.5 V (Note 1) 2
Input Logic 1 (SDA, SCL, A0, A1) min VIH 0.7 x VCC max is VCC + 0.3 V 2
Input Logic 0 (SDA, SCL, A0, A1) max VIL 0.3 x VCC min is -0.3 V 2
Full-Scale Resistor Values RFS0, RFS1, RFS2, RFS3 40 160 kΩ (Note 2) 2
Supply Current DS4424 ICC 250 µA VCC = 5.5V (Note 3) 2
Input Leakage (SDA, SCL) IIL 1 µA VCC = 5.5V 2
Output Leakage (SDA) IL 1 µA 2
Output Current Low (SDA) IOL 3 mA VOL = 0.4V 2
Output Current Low (SDA) IOL 6 mA VOL = 0.6V 2
RFS Voltage VRFS 0.976 V 2
I/O Capacitance CI/O 10 pF 2
Output Voltage for Sinking Current VOUT:SINK 0.5 3.5 V (Note 4) 2
Output Voltage for Sourcing Current VOUT:SOURCE 0 V (Note 4); max is VCC - 0.75 V 2
Full-Scale Sink Output Current IOUT:SINK 50 200 µA (Notes 1, 4) 2
Full-Scale Source Output Current IOUT:SOURCE -200 -50 µA (Notes 1, 4) 2
Output Current Full-Scale Accuracy IOUT:FS -6 6 % +25°C, VCC = 3.3V; using 0.1% RFS resistor (Note 2), VOUT0 = VOUT1 = 1.2V 2
Output Current Temperature Coefficient IOUT:TC -75 75 ppm/°C (Note 5) 2
Output Current Variation Due to Power-Supply Change 0.32 %/V DC source 3
Output Current Variation Due to Power-Supply Change 0.42 %/V DC sink 3
Output Current Variation Due to Output-Voltage Change 0.16 %/V DC source, VOUT measure at 1.2V 3
Output Leakage Current at Zero Current Setting IZERO -1 1 µA 3
Output Current Differential Linearity DNL -0.5 0.5 LSB (Notes 6, 7) 3
Output Current Integral Linearity INL -1 1 LSB (Notes 7, 8) 3
SCL Clock Frequency fSCL 0 400 kHz (Note 9) 3
Bus Free Time Between STOP and START Conditions tBUF 1.3 µs 3
Hold Time (Repeated) START Condition tHD:STA 0.6 µs 3
Low Period of SCL tLOW 1.3 µs 3
High Period of SCL tHIGH 0.6 µs 3
Data Hold Time tDH:DAT 0 0.9 µs 3
Data Setup Time tSU:DAT 100 ns 3
START Setup Time tSU:STA 0.6 µs 3
SDA and SCL Rise Time tR 300 ns (Note 10); min is 20 + 0.1CB 3
SDA and SCL Fall Time tF 300 ns (Note 10); min is 20 + 0.1CB 3
STOP Setup Time tSU:STO 0.6 µs 3
SDA and SCL Capacitive Loading CB 400 pF (Note 10) 3
Voltage Range on VCC, SDA, and SCL -0.5 6 V Relative to Ground 2
Voltage Range on A0, A1, FS0-FS3, OUT0-OUT3 -0.5 V Relative to Ground; max (VCC + 0.5V), not to exceed 6.0V 2
Operating Temperature Range -40 85 °C 2
Storage Temperature Range -55 125 °C 2

CAD (KiCad official)

  • Symbol: DS4424N+T&R
  • Footprint: Package_DFN_QFN:DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
  • 3D model: TDFN-14-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: ds4424n-t-r-etched.step / ds4424n-t-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds4424n-t-r.step / ds4424n-t-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (11 pp, sha256 1a246033d652cc7a, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF