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Texas Instruments New Arrivals, QFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS42MB100TSQ

Texas Instruments · New Arrivals · QFN-36-EP(6x6)

DS42MB100TSQ from Texas Instruments, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DES_1	input	DES_0 and DES_1 select the output pre-emphasis of the switch-side drivers (OUT0±, OUT1±); both are 3.3-V LVCMOS inputs internally pulled high.
2	GND	power_in	Ground reference; each ground pin should connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
3	OUT0+	output	Non-inverting switch-side differential output (CML) with an internal 50 Ω termination to VCC.
4	OUT0-	output	Inverting switch-side differential output (CML) with an internal 50 Ω termination to VCC.
5	VCC	power_in	Supply pin, VCC = 3.3 V ±5% (3.135 V to 3.465 V), to be connected to the VCC plane through a low-inductance path with a 0.01 µF or 0.1 µF X7R size-0402 bypass capacitor.
6	IN0+	input	Non-inverting switch-side MUX differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
7	IN0-	input	Inverting switch-side MUX differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
8	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
9	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
10	DES_0	input	DES_0 and DES_1 select the output pre-emphasis of the switch-side drivers (OUT0±, OUT1±); 3.3-V LVCMOS input internally pulled high.
11	EQL	input	A logic low enables the input equalizer on the line side; internally pulled high, with equalization disabled by default.
12	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
13	VCC	power_in	Supply pin, VCC = 3.3 V ±5%; connect to the VCC plane through a low-inductance path with a 0.01 µF or 0.1 µF X7R size-0402 bypass capacitor.
14	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
15	VCC	power_in	Supply pin, VCC = 3.3 V ±5%; connect to the VCC plane through a low-inductance path with a 0.01 µF or 0.1 µF X7R size-0402 bypass capacitor.
16	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
17	RSV	input	Reserved for factory testing; may be left open, tied to GND, or tied to GND through an external pull-down resistor.
18	DEL_0	input	DEL_0 and DEL_1 select the output pre-emphasis of the line-side drivers (OUT±); 3.3-V LVCMOS input internally pulled high.
19	MUX	input	A logic low selects IN1±; 3.3-V LVCMOS input internally pulled high, with the default state selecting IN0±.
20	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
21	OUT1-	output	Inverting switch-side differential output (CML) with an internal 50 Ω termination to VCC.
22	OUT1+	output	Non-inverting switch-side differential output (CML) with an internal 50 Ω termination to VCC.
23	VCC	power_in	Supply pin, VCC = 3.3 V ±5%; connect to the VCC plane through a low-inductance path with a 0.01 µF or 0.1 µF X7R size-0402 bypass capacitor.
24	IN1-	input	Inverting switch-side MUX differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
25	IN1+	input	Non-inverting switch-side MUX differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
26	LB1	input	A logic low enables the internal loopback path from IN1± to OUT1±; 3.3-V LVCMOS input internally pulled high.
27	DEL_1	input	DEL_0 and DEL_1 select the output pre-emphasis of the line-side drivers (OUT±); 3.3-V LVCMOS input internally pulled high.
28	LB0	input	A logic low enables the internal loopback path from IN0± to OUT0±; 3.3-V LVCMOS input internally pulled high.
29	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
30	OUT+	output	Non-inverting line-side differential output (CML) with an internal 50 Ω termination to VCC.
31	OUT-	output	Inverting line-side differential output (CML) with an internal 50 Ω termination to VCC.
32	VCC	power_in	Supply pin, VCC = 3.3 V ±5%; connect to the VCC plane through a low-inductance path with a 0.01 µF or 0.1 µF X7R size-0402 bypass capacitor.
33	IN+	input	Non-inverting line-side differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
34	IN-	input	Inverting line-side differential input (CML) with an internal 50 Ω connected to an internal reference voltage; input differential termination is 100 Ω.
35	GND	power_in	Ground reference; connect to the ground plane through a low-inductance path, typically a via placed as close as possible to the pad.
36	EQS	input	A logic low enables the input equalizer on the switch side; internally pulled high, with equalization disabled by default.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-36-EP(6x6)
Category	Others
Pins	37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (VCC)	VCC	-0.3		4	V		4
CMOS/TTL input voltage		-0.3			V	Printed maximum is VCC + 0.3 V; not computed	4
CML input/output voltage		-0.3			V	Printed maximum is VCC + 0.3 V; not computed	4
Junction temperature				150	°C		4
Lead temperature (soldering)				260	°C	Soldering, 4 seconds	4
Storage temperature	Tstg	-65		150	°C		4
Supply voltage (VCC, GND)	VCC	3.135	3.3	3.465	V		5
Supply noise amplitude				100	mVPP	10 Hz to 2 GHz	5
Ambient temperature		-40		85	°C		5
Case temperature				100	°C		5
High level input voltage	VIH	2			V	Printed maximum is VCC + 0.3 V; not computed	5
Low level input voltage	VIL	-0.3		0.8	V		5
High level input current	IIH	-10		10	µA	VIN = VCC	5
Low level input current	IIL	75	94	124	µA	VIN = GND	5
Differential input voltage (below 1.25 Gbps)	VID	100		1750	mVP-P	AC coupled; below 1.25 Gbps	5
Differential input voltage (1.25 Gbps to 3.125 Gbps)	VID	100		1560	mVP-P	AC coupled; between 1.25 Gbps and 3.125 Gbps	5
Differential input voltage (above 3.125 Gbps)	VID	100		1200	mVP-P	AC coupled; above 3.125 Gbps	5
Input differential termination	RITD	84	100	116	Ω	On-chip differential termination between IN+ or IN−	5
Driver output differential voltage swing without pre-emphasis	VODB	1100	1300	1500	mVP-P	RL = 100 Ω ±1%; DES_1 = DES_0 = 0; DEL_1 = DEL_0 = 0; running K28.7 pattern at 4.25 Gbps	6
Pre-emphasis width	TPE	125	188	250	ps	Tested at −9 dB pre-emphasis level, DEx[1:0] = 11	6
Output termination	ROTSE	42	50	58	Ω	On-chip termination from OUT+ or OUT− to VCC	6
Mismatch in output termination resistors	ΔROTSE			5	%	Mismatch in output terminations at OUT+ and OUT−	6
Device random jitter (at 0.25 Gbps)	RJ			2	psrms	At 0.25 Gbps; alternating 1-0 pattern; EQ and pre-emphasis disabled	6
Device random jitter (at 1.25 Gbps)	RJ			2	psrms	At 1.25 Gbps; alternating 1-0 pattern; EQ and pre-emphasis disabled	6
Device random jitter (at 4.25 Gbps)	RJ			2	psrms	At 4.25 Gbps; alternating 1-0 pattern; EQ and pre-emphasis disabled	6
Device deterministic jitter	DJ			35	psp-p	Between 0.25 and 4.25 Gbps with PRBS7 pattern, DS42MB100 at −40°C to 85°C; EQ and pre-emphasis disabled	6
Data rate	DR	0.25		4.25	Gbps	Tested with alternating 1-0 pattern	6
Differential low to high transition time	tR			85	ps	Clock-like pattern at 4.25 Gbps, 20% to 80%; pre-emphasis disabled	7
Differential high to low transition time	tF			85	ps	Clock-like pattern at 4.25 Gbps, 20% to 80%; pre-emphasis disabled	7
Pulse skew	tSKP			20	ps	/tPHL − tPLH/	7
Output skew	tSKO			100	ps	Difference in propagation delay among data paths in the same device	7
Part-to-part skew	tSKPP			100	ps	Same output from devices operating under identical conditions	7
MUX switch time	tSM	1.8		6	ns	From VIH or VIL of MUX-control or loopback control to 50% of valid differential output	7
Junction-to-ambient thermal resistance	RθJA		32.8		°C/W	0 airflow; based on 16 thermal relief vias on the DAP pad	5
Junction-to-case (top) thermal resistance	RθJC(top)		14.3		°C/W		5
Junction-to-board thermal resistance	RθJB		6.2		°C/W		5
Junction-to-top characterization parameter	ψJT		0.2		°C/W		5
Junction-to-board characterization parameter	ψJB		6.1		°C/W		5
Junction-to-case (bottom) thermal resistance	RθJC(bot)		1.9		°C/W		5

CAD (KiCad official)

Symbol: DS42MB100TSQ
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: ds42mb100tsq-etched.step / ds42mb100tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds42mb100tsq.step / ds42mb100tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (24 pp, sha256 6ec4383827739115, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS42MB100TSQ

Verified DS42MB100TSQ

Verification log 1 record

DS42MB100TSQ

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance