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DS32ELX0124SQX
Public Made by Adomby adom
Texas Instruments Serializers, Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS32ELX0124SQX
Texas Instruments · Serializers, Deserializers · WQFN-48-EP(7x7)
DS32ELX0124SQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD33 | power_in | 3.3 V supply; recommended range is 3.135 V to 3.465 V (3.3 V typical). |
| 2 | LT_EN | input | DS32ELX0124 only; LVCMOS input that, when held high, enables the retimed serialized high speed output. |
| 3 | GPIO0 | bidirectional | Software configurable LVCMOS I/O pin. |
| 4 | GPIO1 | bidirectional | Software configurable LVCMOS I/O pin. |
| 5 | DC_B | input | LVCMOS DC-balance and Remote Sense pin; see Applications Information for device behavior. |
| 6 | RS | input | LVCMOS DC-balance and Remote Sense pin; see Applications Information for device behavior. |
| 7 | VDD25 | power_in | 2.5 V supply; recommended range is 2.375 V to 2.625 V (2.5 V typical). |
| 8 | N/C | unconnected | No connect for DS32ELX0124. |
| 9 | N/C | unconnected | No connect for DS32ELX0124. |
| 10 | N/C | unconnected | No connect for DS32ELX0124. |
| 11 | GPIO2 | bidirectional | Software configurable LVCMOS I/O pin. |
| 12 | RX_MUX_SEL | input | DS32ELX0124 only; LVCMOS input selecting the deserializer input: 0 = RxIN0+/- selected, 1 = RxIN1+/- selected. |
| 13 | N/C | unconnected | No connect for DS32ELX0124. |
| 14 | VOD_CTRL | input | DS32ELX0124 only; LVCMOS input whose pull-down resistor value sets the loop-through driver output amplitude (VOD). |
| 15 | VDD33 | power_in | 3.3 V supply; recommended range is 3.135 V to 3.465 V (3.3 V typical). |
| 16 | RXIN0+ | input | Non-inverting high speed CML differential input of the deserializer; internally terminated. |
| 17 | RXIN0- | input | Inverting high speed CML differential input of the deserializer; internally terminated. |
| 18 | VDD33 | power_in | 3.3 V supply; recommended range is 3.135 V to 3.465 V (3.3 V typical). |
| 19 | RXIN1+ | input | DS32ELX0124 only; non-inverting high speed CML differential input of the deserializer; internally terminated. |
| 20 | RXIN1- | input | DS32ELX0124 only; inverting high speed CML differential input of the deserializer; internally terminated. |
| 21 | TXOUT+ | output | DS32ELX0124 only; non-inverting retimed serialized high speed CML differential output; internally terminated. |
| 22 | TXOUT- | output | DS32ELX0124 only; inverting retimed serialized high speed CML differential output; internally terminated. |
| 23 | N/C | unconnected | No connect for DS32ELX0124. |
| 24 | N/C | unconnected | No connect for DS32ELX0124. |
| 25 | VDD25 | power_in | 2.5 V supply; recommended range is 2.375 V to 2.625 V (2.5 V typical). |
| 26 | LF_REF | passive | Analog loop filter ground reference. |
| 27 | LF_CP | passive | Analog loop filter capacitor connection. |
| 28 | VDD_PLL | power_in | 3.3 V supply for the PLL. |
| 29 | N/C | unconnected | No connect for DS32ELX0124. |
| 30 | RESET | input | LVCMOS reset pin; held low resets the device, high gives normal operation. |
| 31 | LOCK | output | LVCMOS lock indication output; goes low when the deserializer is locked to the incoming data stream and begins outputting data and clock on RxOUT and RxCLKOUT. |
| 32 | SDA | bidirectional | SMBus compatible data line. |
| 33 | SCK | input | SMBus compatible clock input. |
| 34 | SMB_CS | input | SMBus chip select; when held high, SMBus management control is enabled. |
| 35 | VDD25 | power_in | 2.5 V supply; recommended range is 2.375 V to 2.625 V (2.5 V typical). |
| 36 | VDD33 | power_in | 3.3 V supply; recommended range is 3.135 V to 3.465 V (3.3 V typical). |
| 37 | RXCLKOUT+ | output | Non-inverting LVDS deserializer recovered clock output. |
| 38 | RXCLKOUT- | output | Inverting LVDS deserializer recovered clock output. |
| 39 | RXOUT0+ | output | Non-inverting LVDS deserialized parallel data output. |
| 40 | RXOUT0- | output | Inverting LVDS deserialized parallel data output. |
| 41 | RXOUT1+ | output | Non-inverting LVDS deserialized parallel data output. |
| 42 | RXOUT1- | output | Inverting LVDS deserialized parallel data output. |
| 43 | RXOUT2+ | output | Non-inverting LVDS deserialized parallel data output. |
| 44 | RXOUT2- | output | Inverting LVDS deserialized parallel data output. |
| 45 | RXOUT3+ | output | Non-inverting LVDS deserialized parallel data output. |
| 46 | RXOUT3- | output | Inverting LVDS deserialized parallel data output. |
| 47 | RXOUT4+ | output | Non-inverting LVDS deserialized parallel data output. |
| 48 | RXOUT4- | output | Inverting LVDS deserialized parallel data output. |
| 49 | GND | power_in | Exposed pad (DAP) must be connected to GND by 9 vias. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DS32ELX0124SQX - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ds32elx0124sqx-etched.step/ds32elx0124sqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds32elx0124sqx.step/ds32elx0124sqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
4ffd25a96798cdda, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).