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DS3231SN#T&R

Analog Devices Inc Maxim Integrated · Real Time Clocks · SOIC-16-300mil

DS3231SN#T&R from Analog Devices Inc Maxim Integrated, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 32kHz output Open-drain 32kHz output that requires an external pullup resistor, operates on either supply when enabled, and may be left open if not used.
2 VCC power_in DC power pin for the primary supply, to be decoupled with a 0.1µF to 1.0µF capacitor, and connected to ground if not used.
3 INT/SQW output Open-drain active-low interrupt or square-wave output requiring a pullup to a supply of 5.5V or less, which may be up to 5.5V regardless of VCC, and may be left unconnected if not used.
4 RST bidirectional Open-drain active-low reset input/output that is driven low when VCC falls below VPF and has an internal 50k nominal pullup to VCC, so no external pullup should be connected.
5 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
6 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
7 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
8 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
9 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
10 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
11 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
12 N.C. unconnected No connection pin that the datasheet states must be connected to ground.
13 GND power_in Ground reference pin for the device.
14 VBAT power_in Backup power-supply input to be decoupled with a 0.1µF to 1.0µF low-leakage capacitor, and connected to ground if VBAT is not used.
15 SDA bidirectional Open-drain I2C serial data input/output requiring an external pullup resistor, with the pullup voltage up to 5.5V regardless of the voltage on VCC.
16 SCL input I2C serial clock input used to synchronize data movement, with up to 5.5V allowed regardless of the voltage on VCC.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package SOIC-16-300mil
Category Clock/Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 2.3 3.3 5.5 V 2
Supply Voltage VBAT 2.3 3 5.5 V 2
Logic 0 Input SDA, SCL VIL -0.3 V 2
Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST, INT/SQW Relative to Ground -0.3 6 V Relative to ground 2
Operating Temperature Range (noncondensing) -40 85 °C 2
Junction Temperature 125 °C 2
Storage Temperature Range -40 85 °C 2
Power-Fail Voltage VPF 2.45 2.575 2.7 V 2
Active Supply Current ICCA 200 μA VCC = 3.63V (Notes 3, 4) 2
Active Supply Current ICCA 300 μA VCC = 5.5V (Notes 3, 4) 2
Standby Supply Current ICCS 110 μA VCC = 3.63V; I2C bus inactive, 32kHz output on, SQW output off (Note 4) 2
Standby Supply Current ICCS 170 μA VCC = 5.5V; I2C bus inactive, 32kHz output on, SQW output off (Note 4) 2
Temperature Conversion Current ICCSCONV 575 μA VCC = 3.63V; I2C bus inactive, 32kHz output on, SQW output off 2
Temperature Conversion Current ICCSCONV 650 μA VCC = 5.5V; I2C bus inactive, 32kHz output on, SQW output off 2
Logic 0 Output, 32kHz, INT/SQW, SDA VOL 0.4 V IOL = 3mA 2
Logic 0 Output, RST VOL 0.4 V IOL = 1mA 2
Output Leakage Current 32kHz, INT/SQW, SDA ILO -1 0 1 μA Output high impedance 2
Input Leakage SCL ILI -1 1 μA 2
RST Pin I/O Leakage IOL -200 10 μA RST high impedance (Note 5) 2
VBAT Leakage Current (VCC Active) IBATLKG 25 100 nA VCC active 2
Frequency Stability vs. Temperature (Industrial), 0°C to +40°C f/fOUT -2 2 ppm VCC = 3.3V or VBAT = 3.3V, aging offset = 00h 3
Frequency Stability vs. Temperature (Industrial), >40°C to +85°C f/fOUT -3.5 3.5 ppm VCC = 3.3V or VBAT = 3.3V, aging offset = 00h 3
Temperature Accuracy Temp -3 3 °C VCC = 3.3V or VBAT = 3.3V 3
Crystal Aging, first year f/fO -1 1 ppm After reflow, not production tested 3
Crystal Aging, 0-10 years f/fO -5 5 ppm After reflow, not production tested 3
Active Battery Current IBATA 70 μA VBAT = 3.63V; EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 4) 3
Active Battery Current IBATA 150 μA VBAT = 5.5V; EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 4) 3
Timekeeping Battery Current IBATT 0.84 3 μA VBAT = 3.63V; EOSC = 0, BBSQW = 0, EN32kHz = 1, SCL = SDA = 0V or VBAT (Note 4) 3
Timekeeping Battery Current IBATT 1 3.5 μA VBAT = 5.5V; EOSC = 0, BBSQW = 0, EN32kHz = 1, SCL = SDA = 0V or VBAT (Note 4) 3
Temperature Conversion Current IBATTC 575 μA VBAT = 3.63V; EOSC = 0, BBSQW = 0, SCL = SDA = 0V or VBAT 3
Temperature Conversion Current IBATTC 650 μA VBAT = 5.5V; EOSC = 0, BBSQW = 0, SCL = SDA = 0V or VBAT 3
SCL Clock Frequency fSCL 400 kHz Fast mode 4
SCL Clock Frequency fSCL 0 100 kHz Standard mode 4
Bus Free Time Between STOP and START Conditions tBUF 1.3 μs Fast mode 4
Bus Free Time Between STOP and START Conditions tBUF 4.7 μs Standard mode 4
Hold Time (Repeated) START Condition tHD:STA 0.6 μs Fast mode (Note 6) 4
Hold Time (Repeated) START Condition tHD:STA 4 μs Standard mode (Note 6) 4
Low Period of SCL Clock tLOW 1.3 μs Fast mode 4
Low Period of SCL Clock tLOW 4.7 μs Standard mode 4
High Period of SCL Clock tHIGH 0.6 μs Fast mode 4
High Period of SCL Clock tHIGH 4 μs Standard mode 4
Data Hold Time tHD:DAT 0 0.9 μs Fast mode (Notes 7, 8) 4
Data Setup Time tSU:DAT 100 ns Fast mode (Note 9) 4
Data Setup Time tSU:DAT 250 ns Standard mode (Note 9) 4
Rise Time of Both SDA and SCL Signals tR 300 ns Fast mode (Note 10) 4
Rise Time of Both SDA and SCL Signals tR 1000 ns Standard mode (Note 10) 4
Fall Time of Both SDA and SCL Signals tF 300 ns Fast mode (Note 10) 4
START Setup Time tSU:STA 0.6 μs Fast mode 4
START Setup Time tSU:STA 4.7 μs Standard mode 4
Setup Time for STOP Condition tSU:STO 0.6 μs Fast mode 4
Setup Time for STOP Condition tSU:STO 4.7 μs Standard mode 4
Capacitive Load for Each Bus Line CB 400 pF Note 10 4
Capacitance for SDA, SCL CI/O 10 pF 4
Pulse Width of Spikes That Must Be Suppressed by the Input Filter tSP 30 ns 4
VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 μs 4
Temperature Conversion Time tCONV 125 200 ms 4
Thermal Resistance, Junction-to-Ambient Theta-JA 73 °C/W 18
Thermal Resistance, Junction-to-Case Theta-JC 23 °C/W 18

CAD (KiCad official)

  • Symbol: DS3231SN#T&R
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ds3231sn-t-r-etched.step / ds3231sn-t-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds3231sn-t-r.step / ds3231sn-t-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (20 pp, sha256 ec27766ea72ac63e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF