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DS25CP114TSQX

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Texas Instruments Signal Switches, Multiplexers, Decoders, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS25CP114TSQX

Texas Instruments · Signal Switches, Multiplexers, Decoders · VQFN-40-EP(6x6)

DS25CP114TSQX from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN0+ input Non-inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
2 IN0- input Inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
3 VDD power_in Power supply pin; recommended supply voltage is 3.0 V to 3.6 V (3.3 V typical).
4 IN1+ input Non-inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
5 IN1- input Inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
6 IN2+ input Non-inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
7 IN2- input Inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
8 VDD power_in Power supply pin; recommended supply voltage is 3.0 V to 3.6 V (3.3 V typical).
9 IN3+ input Non-inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
10 IN3- input Inverting high-speed LVDS input; the DS25CP114 has no internal 100 Ω input termination, so it must be terminated externally.
11 EQ2 input LVCMOS receive equalization level select for channel 2, functional regardless of EN_smb state.
12 EQ3 input LVCMOS receive equalization level select for channel 3, functional regardless of EN_smb state.
13 S30 input LVCMOS input selecting which LVDS input routes to OUT3 when EN_smb = 0; non-functional in SMBus mode and must be tied high or low.
14 S31 input LVCMOS input selecting which LVDS input routes to OUT3 when EN_smb = 0; non-functional in SMBus mode and must be tied high or low.
15 VDD power_in Power supply pin; recommended supply voltage is 3.0 V to 3.6 V (3.3 V typical).
16 GND power_in Power ground pin; the center DAP must also be connected to GND for optimum electrical and thermal performance.
17 EN_smb input LVCMOS SMBus enable with internal 20 kΩ pull-down; setting it to 1 selects SMBus mode, and all SMBus registers reset when this pin is toggled.
18 PE3 input LVCMOS transmit pre-emphasis level select for channel 3, functional regardless of EN_smb state.
19 PE2 input LVCMOS transmit pre-emphasis level select for channel 2, functional regardless of EN_smb state.
20 PE1 input LVCMOS transmit pre-emphasis level select for channel 1, functional regardless of EN_smb state.
21 OUT3- output Inverting LVDS output with internal 100 Ω termination to improve return loss.
22 OUT3+ output Non-inverting LVDS output with internal 100 Ω termination to improve return loss.
23 OUT2- output Inverting LVDS output with internal 100 Ω termination to improve return loss.
24 OUT2+ output Non-inverting LVDS output with internal 100 Ω termination to improve return loss.
25 VDD power_in Power supply pin; recommended supply voltage is 3.0 V to 3.6 V (3.3 V typical).
26 OUT1- output Inverting LVDS output with internal 100 Ω termination to improve return loss.
27 OUT1+ output Non-inverting LVDS output with internal 100 Ω termination to improve return loss.
28 OUT0- output Inverting LVDS output with internal 100 Ω termination to improve return loss.
29 OUT0+ output Non-inverting LVDS output with internal 100 Ω termination to improve return loss.
30 VDD power_in Power supply pin; recommended supply voltage is 3.0 V to 3.6 V (3.3 V typical).
31 PE0 input LVCMOS transmit pre-emphasis level select for channel 0, functional regardless of EN_smb state.
32 S21/ADDR3 input LVCMOS input selecting the OUT2 source when EN_smb = 0; in SMBus mode it is the user-set SMBus slave address bit 3.
33 S20/ADDR2 input LVCMOS input selecting the OUT2 source when EN_smb = 0; in SMBus mode it is the user-set SMBus slave address bit 2.
34 S11/ADDR1 input LVCMOS input selecting the OUT1 source when EN_smb = 0; in SMBus mode it is the user-set SMBus slave address bit 1.
35 S10/ADDR0 input LVCMOS input selecting the OUT1 source when EN_smb = 0; in SMBus mode it is the user-set SMBus slave address bit 0.
36 S01/SDA bidirectional LVCMOS input selecting the OUT0 source when EN_smb = 0; in SMBus mode it is the SMBus data pin.
37 S00/SCL input LVCMOS input selecting the OUT0 source when EN_smb = 0; in SMBus mode it is the SMBus clock input.
38 PWDN input LVCMOS power-down pin when EN_smb = 0: low powers the device down and high powers it up; in SMBus mode power is also controlled by Control Register D[7] (SoftPWDN).
39 EQ1 input LVCMOS receive equalization level select for channel 1, functional regardless of EN_smb state.
40 EQ0 input LVCMOS receive equalization level select for channel 0, functional regardless of EN_smb state.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Logic
Pins 41

CAD (KiCad official)

  • Symbol: DS25CP114TSQX
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds25cp114tsqx-etched.step / ds25cp114tsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25cp114tsqx.step / ds25cp114tsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 7bf748a9e0082456, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF