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DS25CP104ATSQX

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Texas Instruments Signal Switches, Multiplexers, Decoders, WQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS25CP104ATSQX

Texas Instruments · Signal Switches, Multiplexers, Decoders · WQFN-40(6x6)

DS25CP104ATSQX from Texas Instruments, in a WQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN0+ input Non-inverting high-speed LVDS input of channel 0, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
2 IN0- input Inverting high-speed LVDS input of channel 0, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
3 VDD power_in Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical).
4 IN1+ input Non-inverting high-speed LVDS input of channel 1, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
5 IN1- input Inverting high-speed LVDS input of channel 1, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
6 IN2+ input Non-inverting high-speed LVDS input of channel 2, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
7 IN2- input Inverting high-speed LVDS input of channel 2, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
8 VDD power_in Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical).
9 IN3+ input Non-inverting high-speed LVDS input of channel 3, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
10 IN3- input Inverting high-speed LVDS input of channel 3, with an internal 100 Ω differential termination on the DS25CP104A (eliminated on the DS25CP114).
11 EQ2 input Receive equalization level select pin for channel 2 (LVCMOS); functional regardless of the EN_smb state.
12 EQ3 input Receive equalization level select pin for channel 3 (LVCMOS); functional regardless of the EN_smb state.
13 S30 input With EN_smb low, selects which LVDS input is routed to OUT3; non-functional in SMBus mode and should be tied high or low.
14 S31 input With EN_smb low, selects which LVDS input is routed to OUT3; non-functional in SMBus mode and should be tied high or low.
15 VDD power_in Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical).
16 GND power_in Power ground pin; connect to the board ground plane.
17 EN_smb input SMBus enable pin with an internal 20 kΩ pulldown; setting it high selects SMBus mode, and all SMBus registers reset when this pin is toggled.
18 PE3 input Transmit pre-emphasis level select pin for output channel 3 (LVCMOS); functional regardless of the EN_smb state.
19 PE2 input Transmit pre-emphasis level select pin for output channel 2 (LVCMOS); functional regardless of the EN_smb state.
20 PE1 input Transmit pre-emphasis level select pin for output channel 1 (LVCMOS); functional regardless of the EN_smb state.
21 OUT3- output Inverting LVDS output of channel 3 with an internal 100 Ω termination.
22 OUT3+ output Non-inverting LVDS output of channel 3 with an internal 100 Ω termination.
23 OUT2- output Inverting LVDS output of channel 2 with an internal 100 Ω termination.
24 OUT2+ output Non-inverting LVDS output of channel 2 with an internal 100 Ω termination.
25 VDD power_in Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical).
26 OUT1- output Inverting LVDS output of channel 1 with an internal 100 Ω termination.
27 OUT1+ output Non-inverting LVDS output of channel 1 with an internal 100 Ω termination.
28 OUT0- output Inverting LVDS output of channel 0 with an internal 100 Ω termination.
29 OUT0+ output Non-inverting LVDS output of channel 0 with an internal 100 Ω termination.
30 VDD power_in Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical).
31 PE0 input Transmit pre-emphasis level select pin for output channel 0 (LVCMOS); functional regardless of the EN_smb state.
32 S21/ADDR3 input With EN_smb low, selects which LVDS input is routed to OUT2; in SMBus mode it is the user-set SMBus slave address input ADDR3.
33 S20/ADDR2 input With EN_smb low, selects which LVDS input is routed to OUT2; in SMBus mode it is the user-set SMBus slave address input ADDR2.
34 S11/ADDR1 input With EN_smb low, selects which LVDS input is routed to OUT1; in SMBus mode it is the user-set SMBus slave address input ADDR1.
35 S10/ADDR0 input With EN_smb low, selects which LVDS input is routed to OUT1; in SMBus mode it is the user-set SMBus slave address input ADDR0.
36 S01/SDA bidirectional In SMBus mode (EN_smb high) this is the SMBus data pin (SDA), and with EN_smb low it is an LVCMOS input-select pin for OUT0.
37 S00/SCL input In SMBus mode (EN_smb high) this is the SMBus clock input (SCL), and with EN_smb low it selects which LVDS input is routed to OUT0.
38 PWDN input With EN_smb low, a low level puts the device in power-down mode; in SMBus mode the device powers up when PWDN is high or the SoftPWDN bit (Control Register D[7]) is set, and powers down only when both are low.
39 EQ1 input Receive equalization level select pin for channel 1 (LVCMOS); functional regardless of the EN_smb state.
40 EQ0 input Receive equalization level select pin for channel 0 (LVCMOS); functional regardless of the EN_smb state.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40(6x6)
Category Logic
Pins 41

CAD (KiCad official)

  • Symbol: DS25CP104ATSQX
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds25cp104atsqx-etched.step / ds25cp104atsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25cp104atsqx.step / ds25cp104atsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 7bf748a9e0082456, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF