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DS25BR440TSQ

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Texas Instruments LVDS ICs, QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS25BR440TSQ

Texas Instruments · LVDS ICs · QFN-40-EP(6x6)

DS25BR440TSQ from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN0+ input Non-inverting high speed LVDS input for channel 0, internally terminated with 100 Ω between IN+ and IN-.
2 IN0- input Inverting high speed LVDS input for channel 0, internally terminated with 100 Ω between IN+ and IN-.
3 VDD power_in Power supply pin, nominal 3.3 V with a recommended range of 3.0 V to 3.6 V.
4 IN1+ input Non-inverting high speed LVDS input for channel 1, internally terminated with 100 Ω between IN+ and IN-.
5 IN1- input Inverting high speed LVDS input for channel 1, internally terminated with 100 Ω between IN+ and IN-.
6 IN2+ input Non-inverting high speed LVDS input for channel 2, internally terminated with 100 Ω between IN+ and IN-.
7 IN2- input Inverting high speed LVDS input for channel 2, internally terminated with 100 Ω between IN+ and IN-.
8 VDD power_in Power supply pin, nominal 3.3 V with a recommended range of 3.0 V to 3.6 V.
9 IN3+ input Non-inverting high speed LVDS input for channel 3, internally terminated with 100 Ω between IN+ and IN-.
10 IN3- input Inverting high speed LVDS input for channel 3, internally terminated with 100 Ω between IN+ and IN-.
11 EQ2 input LVCMOS receive equalization level select for input IN2; L sets equalization OFF and H sets it ON.
12 EQ3 input LVCMOS receive equalization level select for input IN3; L sets equalization OFF and H sets it ON.
13 LOS3 output Open drain loss-of-signal output reporting an open input fault at IN3; external pull-up resistor required.
14 LOS0 output Open drain loss-of-signal output reporting an open input fault at IN0; external pull-up resistor required.
15 VDD power_in Power supply pin, nominal 3.3 V with a recommended range of 3.0 V to 3.6 V.
16 GND power_in Ground pin, together with the exposed die attach pad (DAP) which is also ground.
17 NC unconnected No connect pin that may be left floating.
18 PE3 input LVCMOS transmit pre-emphasis level select for output OUT3; L sets pre-emphasis OFF and H sets it ON.
19 PE2 input LVCMOS transmit pre-emphasis level select for output OUT2; L sets pre-emphasis OFF and H sets it ON.
20 PE1 input LVCMOS transmit pre-emphasis level select for output OUT1; L sets pre-emphasis OFF and H sets it ON.
21 OUT3- output Inverting high speed LVDS output for channel 3, with 100 Ω differential termination between OUT+ and OUT-.
22 OUT3+ output Non-inverting high speed LVDS output for channel 3, with 100 Ω differential termination between OUT+ and OUT-.
23 OUT2- output Inverting high speed LVDS output for channel 2, with 100 Ω differential termination between OUT+ and OUT-.
24 OUT2+ output Non-inverting high speed LVDS output for channel 2, with 100 Ω differential termination between OUT+ and OUT-.
25 VDD power_in Power supply pin, nominal 3.3 V with a recommended range of 3.0 V to 3.6 V.
26 OUT1- output Inverting high speed LVDS output for channel 1, with 100 Ω differential termination between OUT+ and OUT-.
27 OUT1+ output Non-inverting high speed LVDS output for channel 1, with 100 Ω differential termination between OUT+ and OUT-.
28 OUT0- output Inverting high speed LVDS output for channel 0, with 100 Ω differential termination between OUT+ and OUT-.
29 OUT0+ output Non-inverting high speed LVDS output for channel 0, with 100 Ω differential termination between OUT+ and OUT-.
30 VDD power_in Power supply pin, nominal 3.3 V with a recommended range of 3.0 V to 3.6 V.
31 PE0 input LVCMOS transmit pre-emphasis level select for output OUT0; L sets pre-emphasis OFF and H sets it ON.
32 PWDN3 input LVCMOS channel output power down pin for OUT3; when set to L, output OUT3 is powered down while the LOS circuitry on IN3 remains enabled.
33 PWDN2 input LVCMOS channel output power down pin for OUT2; when set to L, output OUT2 is powered down while the LOS circuitry on IN2 remains enabled.
34 PWDN1 input LVCMOS channel output power down pin for OUT1; when set to L, output OUT1 is powered down while the LOS circuitry on IN1 remains enabled.
35 PWDN0 input LVCMOS channel output power down pin for OUT0; when set to L, output OUT0 is powered down while the LOS circuitry on IN0 remains enabled.
36 LOS2 output Open drain loss-of-signal output reporting an open input fault at IN2; external pull-up resistor required.
37 LOS1 output Open drain loss-of-signal output reporting an open input fault at IN1; external pull-up resistor required.
38 PWDN input Device power down pin; when set to L, the device is in power down mode and the LOS circuitry is disabled as well.
39 EQ1 input LVCMOS receive equalization level select for input IN1; L sets equalization OFF and H sets it ON.
40 EQ0 input LVCMOS receive equalization level select for input IN0; L sets equalization OFF and H sets it ON.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-40-EP(6x6)
Category Interface ICs
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VCC) VCC 3 3.3 3.6 V 4
Receiver Differential Input Voltage VID 0 1 V 4
Operating Free Air Temperature TA -40 25 85 °C 4
Supply Voltage -0.3 4 V 4
LVCMOS Input Voltage -0.3 V max VCC + 0.3V 4
LVCMOS Output Voltage -0.3 V max VCC + 0.3V 4
LVDS Input Voltage -0.3 4 V 4
Differential Input Voltage /VID/ 1 V 4
LVDS Output Voltage -0.3 V max VCC + 0.3V 4
LVDS Differential Output Voltage 0 1 V 4
LVDS Output Short Circuit Current Duration 5 ms 4
Junction Temperature 150 °C 4
Storage Temperature Range -65 150 °C 4
Lead Temperature Range Soldering 260 °C Soldering (4 sec.) 4
Maximum Package Power Dissipation at 25°C 2.44 W RTA0040A Package 4
ESD Susceptibility HBM 8 kV Human Body Model 4
ESD Susceptibility MM 250 V Machine Model 4
ESD Susceptibility CDM 1250 V Field Induced Charge Device Model 4
High Level Input Voltage VIH 2 V 4
Low Level Input Voltage VIL 0.8 V 4
High Level Input Current IIH 0 10 μA VIN = 3.6V, VCC = 3.6V 4
Low Level Input Current IIL 0 10 μA VIN = GND, VCC = 3.6V 5
Input Clamp Voltage VCL -1.5 -0.9 V ICL = −18 mA, VCC = 0V 5
Low Level Output Voltage VOL 0.26 0.4 V IOL= 4 mA 5
Input Differential Voltage VID 0 1 V 5
Differential Input High Threshold VTH 0 100 mV VCM = +0.05V or VCC-0.05V 5
Differential Input Low Threshold VTL -100 0 mV 5
Common Mode Voltage Range VCMR 0.05 V VID = 100 mV; max VCC - 0.05 5
Input Current IIN 1 10 μA VIN = +3.6V or 0V, VCC = 3.6V or 0V 5
Differential Output Voltage VOD 250 350 450 mV 5
Change in Magnitude of VOD for Complimentary Output States ΔVOD -35 35 mV RL = 100Ω 5
Offset Voltage VOS 1.05 1.2 1.375 V 5
Change in Magnitude of VOS for Complimentary Output States ΔVOS -35 35 mV RL = 100Ω 5
Output Short Circuit Current OUT to GND IOS -35 -55 mA OUT to GND; magnitude only 5
Output Short Circuit Current OUT to VCC IOS 7 55 mA OUT to VCC; magnitude only 5
Supply Current ICC 162 190 mA PE = OFF, EQ = OFF, PWDN = H 5
Power Down Supply Current ICCZ 55 63 mA PWDN = L 5
Differential Propagation Delay Low to High tPLHD 390 600 ps RL = 100Ω 5
Differential Propagation Delay High to Low tPHLD 400 600 ps RL = 100Ω 5
Pulse Skew tSKD1 10 50 ps 5
Channel to Channel Skew tSKD2 18 65 ps 6
Part to Part Skew tSKD3 50 170 ps 6
Rise Time tLHT 80 160 ps RL = 100Ω 6
Fall Time tHLT 80 160 ps RL = 100Ω 6
Any PWDN to Output Active Time tON 8 20 μs 6
Any PWDN to Output Inactive Time tOFF 5 12 ns 6
Input Capacitance CIN 1.7 pF Any LVDS Input Pin to GND 5
Input Termination Resistor RIN 100 Ω Between IN+ and IN- 5
Output Capacitance COUT 1.2 pF Any LVDS Output Pin to GND 5
Output Termination Resistor ROUT 100 Ω Between OUT+ and OUT- 5
Package Thermal Resistance junction-to-ambient θJA 26.9 °C/W 4
Package Thermal Resistance junction-to-case θJC 3.8 °C/W 4
Derate RTA0040A Package 19.49 mW/°C above +25°C 4

CAD (KiCad official)

  • Symbol: DS25BR440TSQ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds25br440tsq-etched.step / ds25br440tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25br440tsq.step / ds25br440tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 bdcc2e95f36733ce, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF