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DS25BR120TSD

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Texas Instruments LVDS ICs, SON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS25BR120TSD

Texas Instruments · LVDS ICs · SON-8-EP(3x3)

DS25BR120TSD from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE1 input Pre-emphasis select pin (LVCMOS input, VIH 2.0 V to VCC, VIL GND to 0.8 V) that together with PE0 sets Off/Low/Medium/High pre-emphasis.
2 IN+ input Non-inverting LVDS input with internal 100Ω termination between IN+ and IN-, accepting LVDS, CML and LVPECL levels.
3 IN- input Inverting LVDS input with internal 100Ω termination between IN+ and IN-, accepting LVDS, CML and LVPECL levels.
4 PE0 input Pre-emphasis select pin (LVCMOS input, VIH 2.0 V to VCC, VIL GND to 0.8 V) that together with PE1 sets Off/Low/Medium/High pre-emphasis.
5 NC unconnected No connect pin.
6 OUT- output Inverting LVDS output with internal 100Ω termination between OUT+ and OUT-, VOD 250 to 450 mV into 100Ω.
7 OUT+ output Non-inverting LVDS output with internal 100Ω termination between OUT+ and OUT-, VOD 250 to 450 mV into 100Ω.
8 VCC power_in Power supply pin, 3.0 V to 3.6 V recommended operating range (3.3 V typical).
9 GND power_in Ground pad (die attach pad, DAP) that must be soldered to the board for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Communication Interface Chip/UART/485/232
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VCC) VCC 3 3.3 3.6 V 3
Receiver Differential Input Voltage (VID) VID 0 1 V 3
Operating Free Air Temperature (TA) TA -40 25 85 °C 3
Supply Voltage (VCC) VCC -0.3 4 V 3
LVCMOS Input Voltage (PE0, PE1) -0.3 V 3
LVDS Input Voltage (IN+, IN-) -0.3 4 V 3
Differential Input Voltage /VID/ /VID/ 1 V 3
LVDS Output Voltage (OUT+, OUT-) -0.3 V 3
LVDS Differential Output Voltage ((OUT+) - (OUT-)) 0 1 V 3
LVDS Output Short Circuit Current Duration 5 ms 3
Junction Temperature 150 °C 3
Storage Temperature Range -65 150 °C 3
Lead Temperature Range Soldering 260 °C 4 sec. 3
Maximum Package Power Dissipation at 25°C 2.08 W NGQ Package, at 25°C 3
Input Voltage High Level (VIH) LVCMOS VIH 2 V 3
Low Level Input Voltage (VIL) VIL 0.8 V 3
High Level Input Current (IIH) IIH -10 0 10 μA VIN = 3.6V; VCC = 3.6V 3
Low Level Input Current (IIL) IIL -10 0 10 μA VIN = GND; VCC = 3.6V 3
Input Clamp Voltage (VCL) VCL -1.5 -0.9 V ICL = -18 mA, VCC = 0V 4
Differential Output Voltage (VOD) VOD 250 350 450 mV 4
Change in Magnitude of VOD for Complimentary Output States (ΔVOD) ΔVOD -35 35 mV RL = 100Ω 4
Offset Voltage (VOS) VOS 1.05 1.2 1.375 V 4
Change in Magnitude of VOS for Complimentary Output States (ΔVOS) ΔVOS -35 35 mV RL = 100Ω 4
Output Short Circuit Current (IOS) OUT to GND IOS -55 -35 mA OUT to GND; PE0 = PE1 = 0 4
Output Short Circuit Current (IOS) OUT to VCC IOS 7 55 mA OUT to VCC; PE0 = PE1 = 0 4
Input Differential Voltage (VID) VID 0 1 V 4
Differential Input High Threshold (VTH) VTH 0 100 mV VCM = +0.05V or VCC-0.05V 4
Differential Input Low Threshold (VTL) VTL -100 0 mV 4
Common Mode Voltage Range (VCMR) VCMR 0.05 V VID = 100 mV 4
Input Current (IIN) IIN -10 10 μA VIN = 3.6V or 0V; VCC = 3.6V or 0V 4
Supply Current (ICC) ICC 35 43 mA PE0 = 0, PE1 = 0 4
Differential Propagation Delay High to Low (tPHLD) tPHLD 350 465 ps RL = 100Ω 4
Differential Propagation Delay Low to High (tPLHD) tPLHD 350 465 ps RL = 100Ω 4
Pulse Skew /tPLHD - tPHLD/ tSKD1 45 100 ps 4
Part to Part Skew tSKD2 45 150 ps 4
Rise Time tLHT 80 150 ps RL = 100Ω 4
Fall Time tHLT 80 150 ps RL = 100Ω 4
Random Jitter (RMS Value), 2.5 Gbps, PE off tRJ1A 0.5 1 ps VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 0, PE1 = 0 5
Deterministic Jitter (Peak to Peak), 2.5 Gbps, PE off tDJ1A 9 31 ps VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 0, PE1 = 0 5
Deterministic Jitter (Peak to Peak), K28.5 3.125 Gbps, PE off tDJ2A 16 40 ps K28.5 (NRZ) 3.125 Gbps; PE0 = 0, PE1 = 0 5
Total Jitter (Peak to Peak), 2.5 Gbps, PE off tTJ1A 0.05 0.13 UIP-P VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 0, PE1 = 0 5
Total Jitter (Peak to Peak), PRBS-23 3.125 Gbps, PE off tTJ2A 0.09 0.16 UIP-P PRBS-23 (NRZ) 3.125 Gbps; PE0 = 0, PE1 = 0 5
Deterministic Jitter (Peak to Peak), 2.5 Gbps, PE low tDJ1B 17 31 ps VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 1, PE1 = 0 5
Deterministic Jitter (Peak to Peak), K28.5 3.125 Gbps, PE low tDJ2B 18 40 ps K28.5 (NRZ) 3.125 Gbps; PE0 = 1, PE1 = 0 5
Total Jitter (Peak to Peak), 2.5 Gbps, PE low tTJ1B 0.09 0.14 UIP-P VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 1, PE1 = 0 5
Total Jitter (Peak to Peak), PRBS-23 3.125 Gbps, PE low tTJ2B 0.12 0.19 UIP-P PRBS-23 (NRZ) 3.125 Gbps; PE0 = 1, PE1 = 0 5
Deterministic Jitter (Peak to Peak), 2.5 Gbps, PE medium tDJ1C 21 44 ps VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 0, PE1 = 1 5
Deterministic Jitter (Peak to Peak), K28.5 3.125 Gbps, PE medium tDJ2C 27 48 ps K28.5 (NRZ) 3.125 Gbps; PE0 = 0, PE1 = 1 5
Total Jitter (Peak to Peak), 2.5 Gbps, PE medium tTJ1C 0.09 0.16 UIP-P VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 0, PE1 = 1 5
Total Jitter (Peak to Peak), PRBS-23 3.125 Gbps, PE medium tTJ2C 0.13 0.23 UIP-P PRBS-23 (NRZ) 3.125 Gbps; PE0 = 0, PE1 = 1 5
Deterministic Jitter (Peak to Peak), 2.5 Gbps, PE high tDJ1D 30 65 ps VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 1, PE1 = 1 5
Deterministic Jitter (Peak to Peak), K28.5 3.125 Gbps, PE high tDJ2D 30 58 ps K28.5 (NRZ) 3.125 Gbps; PE0 = 1, PE1 = 1 5
Total Jitter (Peak to Peak), 2.5 Gbps, PE high tTJ1D 0.09 0.2 UIP-P VID = 350 mV; VCM = 1.2V; 2.5 Gbps; PE0 = 1, PE1 = 1 5
Total Jitter (Peak to Peak), PRBS-23 3.125 Gbps, PE high tTJ2D 0.13 0.22 UIP-P PRBS-23 (NRZ) 3.125 Gbps; PE0 = 1, PE1 = 1 5
Output Capacitance (COUT) COUT 1.2 pF Any LVDS Output Pin to GND 4
Output Termination Resistor (ROUT) ROUT 100 Ω Between OUT+ and OUT- 4
Input Capacitance (CIN) CIN 1.7 pF Any LVDS Input Pin to GND 4
Input Termination Resistor (RIN) RIN 100 Ω Between IN+ and IN- 4
Package Thermal Resistance (θJA) θJA 60 °C/W 3
Package Thermal Resistance (θJC) θJC 12.3 °C/W 3

CAD (KiCad official)

  • Symbol: DS25BR120TSD
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: ds25br120tsd-etched.step / ds25br120tsd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds25br120tsd.step / ds25br120tsd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 6297850bf9c604eb, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF