component

DS250DF230RTVR

Public Made by Adom

by adom

Texas Instruments Interface - Specialized, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceds250df230rtvrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DS250DF230RTVR

Texas Instruments · Interface - Specialized · WQFN-32-EP(5x5)

DS250DF230RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
2 TX1N output Inverting 50-Ω driver output that must be AC-coupled.
3 TX1P output Non-inverting 50-Ω driver output that must be AC-coupled.
4 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
5 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
6 TX0N output Inverting 50-Ω driver output that must be AC-coupled.
7 TX0P output Non-inverting 50-Ω driver output that must be AC-coupled.
8 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
9 READ_EN_N input 3.3-V tolerant LVCMOS input with weak pull-up to VDD; in SMBus master mode asserting it low starts the EEPROM read, and in SMBus slave mode asserting it low holds the device in reset, so it must be pulled high or left floating for normal operation.
10 CAL_CLK_IN input 2.5-V LVCMOS input for a 30.72-MHz (±100 ppm) single-ended calibration clock from an external oscillator, which also supports 25 MHz (±100 ppm) when the registers are programmed accordingly.
11 VDD power_in 2.5-V supply (2.375 V to 2.625 V, ±5%) that must be connected through a low-resistance path to the board VDD plane with decoupling capacitors placed as close as possible.
12 THR/TEST1 input Four-level strap that selects the SMBus interface voltage (1 kΩ to VDD or float for 1.8 V, 1 kΩ to GND for 2.5 V/3.3 V) and is a reserved TI test pin in TI test mode.
13 TEST0/RCK0 bidirectional 2.5-V LVCMOS pin that is reserved for TI test mode, is an input by default during normal operation (may be floated, tied to GND, or driven by a 2.5-V max output), and can be configured to output the CH0 recovered clock.
14 VDD power_in 2.5-V supply (2.375 V to 2.625 V, ±5%) that must be connected through a low-resistance path to the board VDD plane with decoupling capacitors placed as close as possible.
15 EN_SMB input Four-level 2.5-V input that selects SMBus master mode (float) or SMBus slave mode (1 kΩ to VDD), with 10 kΩ to GND reserved for TI test mode.
16 ADDR1 input Four-level strap read at power-up that sets part of the SMBus address (0 = 1 kΩ to GND, R = 10 kΩ to GND, F = float, 1 = 1 kΩ to VDD), allowing 16 unique device addresses together with ADDR0.
17 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
18 RX0P input Non-inverting differential input to the equalizer with an on-chip 100-Ω termination between RX0P and RX0N, which must be AC-coupled.
19 RX0N input Inverting differential input to the equalizer with an on-chip 100-Ω termination between RX0P and RX0N, which must be AC-coupled.
20 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
21 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
22 RX1P input Non-inverting differential input to the equalizer with an on-chip 100-Ω termination between RX1P and RX1N, which must be AC-coupled.
23 RX1N input Inverting differential input to the equalizer with an on-chip 100-Ω termination between RX1P and RX1N, which must be AC-coupled.
24 GND power_in Ground reference that must be connected through a low-resistance path to the board GND plane.
25 ADDR0 input Four-level strap read at power-up that sets part of the SMBus address (0 = 1 kΩ to GND, R = 10 kΩ to GND, F = float, 1 = 1 kΩ to VDD), allowing 16 unique device addresses together with ADDR1.
26 INT_N output 3.3-V tolerant, open-drain, active-low interrupt output that needs a 2-kΩ to 5-kΩ pull-up and may be wire-ORed with other devices' INT_N pins.
27 VDD power_in 2.5-V supply (2.375 V to 2.625 V, ±5%) that must be connected through a low-resistance path to the board VDD plane with decoupling capacitors placed as close as possible.
28 SDC bidirectional 3.3-V tolerant SMBus clock input / open-drain clock output that requires an external 2-kΩ to 5-kΩ pull-up resistor.
29 SDA bidirectional 3.3-V tolerant SMBus data input / open-drain output that requires an external 2-kΩ to 5-kΩ pull-up resistor.
30 VDD power_in 2.5-V supply (2.375 V to 2.625 V, ±5%) that must be connected through a low-resistance path to the board VDD plane with decoupling capacitors placed as close as possible.
31 CAL_CLK_OUT output 2.5-V LVCMOS buffered replica of CAL_CLK_IN intended for daisy-chaining up to 20 or more devices.
32 ALL_DONE_N output 2.5-V LVCMOS output that in SMBus master mode is low when the EEPROM load succeeded and is high when it failed or is incomplete, and in SMBus slave mode reflects the status of READ_EN_N.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS250DF230RTVR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds250df230rtvr-etched.step / ds250df230rtvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds250df230rtvr.step / ds250df230rtvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (120 pp, sha256 7e3ecd737487c2aa, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF