component

DS16EV5110SQX

Public Made by Adom

by adom

Texas Instruments Interface - Specialized, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ds16ev5110sqxfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 19d ago
viewers ds16ev5110sqx: viewers · Ray 19d ago
ds16ev5110sqx-etched.glb ds16ev5110sqx: factory component page (tier=lcsc) · Ray 19d ago
ds16ev5110sqx-etched.step ds16ev5110sqx: factory component page (tier=lcsc) · Ray 19d ago
ds16ev5110sqx-hero.glb ds16ev5110sqx: hero GLB from the etched model (keeps the MPN mark) · Ray 19d ago
ds16ev5110sqx-hero.overlay.json Publish 0.1.0 · Ray 19d ago
ds16ev5110sqx.glb Publish 0.1.0 · Ray 19d ago
ds16ev5110sqx.kicad_mod Publish 0.1.0 · Ray 19d ago
ds16ev5110sqx.kicad_sym Publish 0.1.0 · Ray 19d ago
ds16ev5110sqx.lbr Publish 0.1.0 · Ray 19d ago
ds16ev5110sqx.step Publish 0.1.0 · Ray 19d ago
package.json Publish 0.1.0 · Ray 19d ago
page.json Set visibility: public · Ray 19d ago
README.md Publish 0.1.0 · Ray 19d ago

DS16EV5110SQX

Texas Instruments · Interface - Specialized · WQFN-48-EP(7x7)

DS16EV5110SQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C_IN- input Inverting TMDS clock input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
2 C_IN+ input Non-inverting TMDS clock input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
3 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
4 D_IN0- input Inverting TMDS data channel 0 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
5 D_IN0+ input Non-inverting TMDS data channel 0 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
6 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
7 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
8 D_IN1- input Inverting TMDS data channel 1 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
9 D_IN1+ input Non-inverting TMDS data channel 1 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
10 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
11 D_IN2- input Inverting TMDS data channel 2 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
12 D_IN2+ input Non-inverting TMDS data channel 2 input to the equalizer, with an on-chip 50Ω termination resistor to VDD.
13 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
14 BST_1 input LVCMOS equalizer boost select bit 1, internally pulled Low.
15 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
16 CS input SMBus chip select; High enables the equalizer SMBus register, Low disables it, internally pulled Low and gated with SDC.
17 SDC input SMBus clock input, internally pulled High to 3.3V with High-Z pull up.
18 SDA bidirectional SMBus data input/output, internally pulled High to 3.3V with High-Z pull up.
19 Reserv unconnected Reserved; do not connect.
20 Reserv unconnected Reserved; do not connect.
21 FEB input Force External Boost; High sets boost from the BST_[0:2] pins, Low sets boost through SMBus, internally pulled High.
22 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
23 BST_0 input LVCMOS equalizer boost select bit 0, internally pulled Low.
24 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
25 D_OUT2+ output Non-inverting open-collector CML TMDS data channel 2 output from the equalizer.
26 D_OUT2- output Inverting open-collector CML TMDS data channel 2 output from the equalizer.
27 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
28 D_OUT1+ output Non-inverting open-collector CML TMDS data channel 1 output from the equalizer.
29 D_OUT1- output Inverting open-collector CML TMDS data channel 1 output from the equalizer.
30 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
31 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
32 D_OUT0+ output Non-inverting open-collector CML TMDS data channel 0 output from the equalizer.
33 D_OUT0- output Inverting open-collector CML TMDS data channel 0 output from the equalizer.
34 GND power_in Ground reference tied to a solid ground plane through a low impedance path.
35 C_OUT+ output Non-inverting open-collector CML TMDS clock output from the equalizer.
36 C_OUT- output Inverting open-collector CML TMDS clock output from the equalizer.
37 BST_2 input LVCMOS equalizer boost select bit 2, internally pulled Low.
38 Reserv unconnected Reserved; do not connect.
39 Reserv unconnected Reserved; do not connect.
40 Reserv unconnected Reserved; do not connect.
41 Reserv unconnected Reserved; do not connect.
42 Reserv unconnected Reserved; do not connect.
43 Reserv unconnected Reserved; do not connect.
44 EN input Enable equalizer input; High selects normal operation, Low selects standby mode, internally pulled High and global to all channels.
45 SD output LVCMOS clock channel signal detect output that goes High when signal is detected.
46 VDD power_in 3.3V supply tied to the VDD plane through a low inductance path with a 0.1µF bypass capacitor to GND.
47 Reserv unconnected Reserved; do not connect.
48 Reserv unconnected Reserved; do not connect.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

CAD (KiCad official)

  • Symbol: DS16EV5110SQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds16ev5110sqx-etched.step / ds16ev5110sqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds16ev5110sqx.step / ds16ev5110sqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 5ed3c38333aa8729, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF