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DS16EV5110ASQ

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Texas Instruments Video Interface ICs, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS16EV5110ASQ

Texas Instruments · Video Interface ICs · WQFN-48-EP(7x7)

DS16EV5110ASQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C_IN− input Inverting TMDS Clock input with on-chip 50Ω terminating resistor to VDD.
2 C_IN+ input Non-inverting TMDS Clock input with on-chip 50Ω terminating resistor to VDD.
3 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
4 D_IN0− input Inverting TMDS Data input channel 0 with on-chip 50Ω terminating resistor to VDD.
5 D_IN0+ input Non-inverting TMDS Data input channel 0 with on-chip 50Ω terminating resistor to VDD.
6 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
7 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
8 D_IN1− input Inverting TMDS Data input channel 1 with on-chip 50Ω terminating resistor to VDD.
9 D_IN1+ input Non-inverting TMDS Data input channel 1 with on-chip 50Ω terminating resistor to VDD.
10 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
11 D_IN2− input Inverting TMDS Data input channel 2 with on-chip 50Ω terminating resistor to VDD.
12 D_IN2+ input Non-inverting TMDS Data input channel 2 with on-chip 50Ω terminating resistor to VDD.
13 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
14 BST_1 input Boost level select bit 1 (internally pulled Low) for equalizer configuration.
15 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
16 CS input SMBus Chip Select (internally pulled Low); enabled when held High, disabled when held Low.
17 SDC input SMBus Clock Input (internally pulled High to 3.3V with High-Z pull-up).
18 SDA bidirectional SMBus Data line (internally pulled High to 3.3V with High-Z pull-up).
19 Reserv unconnected Reserved pin; do not connect.
20 Reserv unconnected Reserved pin; do not connect.
21 FEB input Force External Boost (internally pulled High); High enables boost control via BST pins, Low enables SMBus control.
22 GND power_in Ground reference requiring solid ground plane connection.
23 BST_0 input Boost level select bit 0 (internally pulled Low) for equalizer configuration.
24 GND power_in Ground reference requiring solid ground plane connection.
25 D_OUT2+ tri_state Non-inverting TMDS Data output channel 2 (open-collector).
26 D_OUT2− tri_state Inverting TMDS Data output channel 2 (open-collector).
27 GND power_in Ground reference requiring solid ground plane connection.
28 D_OUT1+ tri_state Non-inverting TMDS Data output channel 1 (open-collector).
29 D_OUT1- tri_state Inverting TMDS Data output channel 1 (open-collector).
30 GND power_in Ground reference requiring solid ground plane connection.
31 GND power_in Ground reference requiring solid ground plane connection.
32 D_OUT0+ tri_state Non-inverting TMDS Data output channel 0 (open-collector).
33 D_OUT0− tri_state Inverting TMDS Data output channel 0 (open-collector).
34 GND power_in Ground reference requiring solid ground plane connection.
35 C_OUT+ tri_state Non-inverting TMDS Clock output (open-collector).
36 C_OUT- tri_state Inverting TMDS Clock output (open-collector).
37 BST_2 input Boost level select bit 2 (internally pulled Low) for equalizer configuration.
38 Reserv unconnected Reserved pin; do not connect.
39 Reserv unconnected Reserved pin; do not connect.
40 Reserv unconnected Reserved pin; do not connect.
41 Reserv unconnected Reserved pin; do not connect.
42 Reserv unconnected Reserved pin; do not connect.
43 Reserv unconnected Reserved pin; do not connect.
44 EN input Enable Equalizer input (internally pulled High); High for normal operation, Low for standby mode.
45 SD output Clock Channel Signal Detect Output; produces High when signal is detected.
46 VDD power_in Power supply pin (3.0V to 3.6V operating range) requiring low inductance connection and 0.1µF bypass capacitor.
47 Reserv unconnected Reserved pin; do not connect.
48 Reserv unconnected Reserved pin; do not connect.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS16EV5110ASQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds16ev5110asq-etched.step / ds16ev5110asq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds16ev5110asq.step / ds16ev5110asq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 8197f99e1a4a9be5, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF