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DS15MB200TSQX
Public Made by Adomby adom
Texas Instruments LVDS ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS15MB200TSQX
Texas Instruments · LVDS ICs · QFN-48-EP(7x7)
DS15MB200TSQX from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N/C | unconnected | Listed as N/C (no connection) in the pin figure; the datasheet gives no function for this pin. |
| 2 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 3 | GND | power_in | Ground reference for LVDS and CMOS circuitry. |
| 4 | ENL_1 | input | LVTTL output enable for the Line-side outputs of channel 1; each Line-side output driver has its own enable pin. |
| 5 | PREL_1 | input | LVTTL output pre-emphasis control for the Line-side outputs of channel 1, switching pre-emphasis off (0) or on (1). |
| 6 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 7 | LO_1+ | output | Line-side channel 1 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 8 | LO_1- | output | Line-side channel 1 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 9 | LI_1+ | input | Line-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 10 | LI_1- | input | Line-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 11 | MUX_S1 | input | LVTTL mux select control for channel 1, choosing whether Switch-side input A or B is passed to the Line side. |
| 12 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 13 | ENA_1 | input | LVTTL output enable for the Switch A-side outputs of channel 1; each A-side and B-side output driver has its own enable pin. |
| 14 | ENB_1 | input | LVTTL output enable for the Switch B-side outputs of channel 1; each A-side and B-side output driver has its own enable pin. |
| 15 | SOA_1+ | output | Switch A-side channel 1 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 16 | SOA_1- | output | Switch A-side channel 1 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 17 | SOB_1+ | output | Switch B-side channel 1 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 18 | SOB_1- | output | Switch B-side channel 1 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 19 | SIA_1+ | input | Switch A-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 20 | SIA_1- | input | Switch A-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 21 | SIB_1+ | input | Switch B-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 22 | SIB_1- | input | Switch B-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 23 | PREA_1 | input | LVTTL output pre-emphasis control for the Switch A-side output driver of channel 1, switching pre-emphasis off (0) or on (1). |
| 24 | PREB_1 | input | LVTTL output pre-emphasis control for the Switch B-side output driver of channel 1, switching pre-emphasis off (0) or on (1). |
| 25 | PREB_0 | input | LVTTL output pre-emphasis control for the Switch B-side output driver of channel 0, switching pre-emphasis off (0) or on (1). |
| 26 | PREA_0 | input | LVTTL output pre-emphasis control for the Switch A-side output driver of channel 0, switching pre-emphasis off (0) or on (1). |
| 27 | SIB_0- | input | Switch B-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 28 | SIB_0+ | input | Switch B-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 29 | SIA_0- | input | Switch A-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 30 | SIA_0+ | input | Switch A-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 31 | SOB_0- | output | Switch B-side channel 0 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 32 | SOB_0+ | output | Switch B-side channel 0 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 33 | SOA_0- | output | Switch A-side channel 0 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 34 | SOA_0+ | output | Switch A-side channel 0 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 35 | ENB_0 | input | LVTTL output enable for the Switch B-side outputs of channel 0; each B-side output driver has its own enable pin. |
| 36 | ENA_0 | input | LVTTL output enable for the Switch A-side outputs of channel 0; each A-side output driver has its own enable pin. |
| 37 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 38 | MUX_S0 | input | LVTTL mux select control for channel 0, choosing whether Switch-side input A or B is passed to the Line side. |
| 39 | LI_0- | input | Line-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 40 | LI_0+ | input | Line-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible. |
| 41 | LO_0- | output | Line-side channel 0 inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 42 | LO_0+ | output | Line-side channel 0 non-inverting LVDS differential output, LVDS compatible, point-to-point use only. |
| 43 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 44 | PREL_0 | input | LVTTL output pre-emphasis control for the Line-side outputs of channel 0, switching pre-emphasis off (0) or on (1). |
| 45 | ENL_0 | input | LVTTL output enable for the Line-side outputs of channel 0; each Line-side output driver has its own enable pin. |
| 46 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 47 | GND | power_in | Ground reference for LVDS and CMOS circuitry. |
| 48 | VDD | power_in | Supply pin; VDD = 3.3V ±0.3V. |
| 49 | DAP (GND) | power_in | Exposed die attach pad, the primary GND connection for the WQFN package; it should be soldered to the ground plane with at least 4 vias. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DS15MB200TSQX - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ds15mb200tsqx-etched.step/ds15mb200tsqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds15mb200tsqx.step/ds15mb200tsqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
5af4c72a7d27eccb, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).