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DS15MB200TSQ

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Texas Instruments LVDS ICs, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS15MB200TSQ

Texas Instruments · LVDS ICs · WQFN-48-EP(7x7)

DS15MB200TSQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N/C unconnected No connect pin, shown as N/C in the connection diagram.
2 VDD power_in Power supply, VDD = 3.3V ±0.3V.
3 GND power_in Ground reference for LVDS and CMOS circuitry.
4 ENL_1 input LVTTL output enable for the Channel 1 Line-side output driver.
5 PREL_1 input LVTTL pre-emphasis control for the Channel 1 Line-side output (0 = 0%, 1 = 100%).
6 VDD power_in Power supply, VDD = 3.3V ±0.3V.
7 LO_1+ tri_state Line-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop), with internal 100Ω source termination.
8 LO_1- tri_state Line-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop), with internal 100Ω source termination.
9 LI_1+ input Line-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
10 LI_1- input Line-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
11 MUX_S1 input LVTTL mux select for Channel 1 choosing Switch-side input A or B to pass to the Line-side.
12 VDD power_in Power supply, VDD = 3.3V ±0.3V.
13 ENA_1 input LVTTL output enable for the Channel 1 Switch A-side output driver.
14 ENB_1 input LVTTL output enable for the Channel 1 Switch B-side output driver.
15 SOA_1+ tri_state Switch A-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop).
16 SOA_1- tri_state Switch A-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop).
17 SOB_1+ tri_state Switch B-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop).
18 SOB_1- tri_state Switch B-side Channel 1 LVDS-compatible differential output, point-to-point only (no multidrop).
19 SIA_1+ input Switch A-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
20 SIA_1- input Switch A-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
21 SIB_1+ input Switch B-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
22 SIB_1- input Switch B-side Channel 1 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
23 PREA_1 input LVTTL pre-emphasis control for the Channel 1 Switch A-side output (0 = 0%, 1 = 100%).
24 PREB_1 input LVTTL pre-emphasis control for the Channel 1 Switch B-side output (0 = 0%, 1 = 100%).
25 PREB_0 input LVTTL pre-emphasis control for the Channel 0 Switch B-side output (0 = 0%, 1 = 100%).
26 PREA_0 input LVTTL pre-emphasis control for the Channel 0 Switch A-side output (0 = 0%, 1 = 100%).
27 SIB_0- input Switch B-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
28 SIB_0+ input Switch B-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
29 SIA_0- input Switch A-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
30 SIA_0+ input Switch A-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
31 SOB_0- tri_state Switch B-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop).
32 SOB_0+ tri_state Switch B-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop).
33 SOA_0- tri_state Switch A-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop).
34 SOA_0+ tri_state Switch A-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop).
35 ENB_0 input LVTTL output enable for the Channel 0 Switch B-side output driver.
36 ENA_0 input LVTTL output enable for the Channel 0 Switch A-side output driver.
37 VDD power_in Power supply, VDD = 3.3V ±0.3V.
38 MUX_S0 input LVTTL mux select for Channel 0 choosing Switch-side input A or B to pass to the Line-side.
39 LI_0- input Line-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
40 LI_0+ input Line-side Channel 0 differential input, LVDS, Bus LVDS, CML or LVPECL compatible.
41 LO_0- tri_state Line-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop), with internal 100Ω source termination.
42 LO_0+ tri_state Line-side Channel 0 LVDS-compatible differential output, point-to-point only (no multidrop), with internal 100Ω source termination.
43 VDD power_in Power supply, VDD = 3.3V ±0.3V.
44 PREL_0 input LVTTL pre-emphasis control for the Channel 0 Line-side output (0 = 0%, 1 = 100%).
45 ENL_0 input LVTTL output enable for the Channel 0 Line-side output driver.
46 VDD power_in Power supply, VDD = 3.3V ±0.3V.
47 GND power_in Ground reference for LVDS and CMOS circuitry.
48 VDD power_in Power supply, VDD = 3.3V ±0.3V.
49 DAP power_in Exposed die attach pad and primary ground connection, to be tied to the ground plane with at least 4 vias for AC and thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD -0.3 4 V 5
CMOS Input Voltage -0.3 V -0.3 to (VDD+0.3) 5
LVDS Output Short Circuit Current 40 mA 5
Junction Temperature 150 °C 5
Storage Temperature -65 150 °C 5
Lead Temperature 260 °C Solder, 4sec 5
Max Pkg Power Capacity 5.2 W @ 25°C 5
Thermal Resistance θJA 24 °C/W 5
Supply Voltage VCC 3 3.6 V 5
Input Voltage VI 0 3.6 V 0 to VCC; VID max < 2.4V 5
Output Voltage VO 0 3.6 V 0 to VCC 5
Operating Temperature TA -40 85 °C Industrial 5
High Level Input Voltage VIH 2 3.3 V max printed as VDD 6
Low Level Input Voltage VIL 0 0.8 V min printed as GND 6
High Level Input Current IIH -10 10 µA VIN = VDD = VDDMAX 6
High Level Input Current IIHR 40 200 µA PREA_n, PREB_n, PREL_n 6
Low Level Input Current IIL -10 10 µA VIN = VSS, VDD = VDDMAX 6
Input Clamp Voltage VCL -1.5 -0.8 V ICL = -18 mA 6
Differential Input High Threshold VTH 0 100 mV VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V 6
Differential Input Low Threshold VTL -100 0 mV VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V 6
Differential Input Voltage VID 100 2400 mV VCM = 0.8V to 3.55V, VDD = 3.6V 6
Common Mode Voltage Range VCMR 0.05 3.55 V VID = 150 mV, VDD = 3.6V 6
Input Current IIN -15 15 µA VIN = 3.6V, VDD = VDDMAX or 0V 6
Differential Output Voltage VOD 250 360 500 mV RL is the internal 100Ω between OUT+ and OUT-, 0% Pre-emphasis 6
Change in VOD between Complementary States ΔVOD -35 35 mV 6
Offset Voltage VOS 1.05 1.22 1.475 V 6
Change in VOS between Complementary States ΔVOS -35 35 mV 6
Output Short Circuit Current IOS -21 -40 mA OUT+ or OUT- Short to GND 6
Supply Current ICC 225 275 mA All inputs and outputs enabled and active, terminated with external load of 100Ω between OUT+ and OUT- 6
Supply Current - Powerdown Mode ICCZ 0.6 4 mA ENA_0 = ENB_0 = ENL_0 = ENA_1 = ENB_1 = ENL_1 = L 6
Differential Low to High Transition Time tLHT 170 250 ps Alternating 1 and 0 pattern at 200 Mb/s, 20% to 80% of VOD 6
Differential High to Low Transition Time tHLT 170 250 ps Alternating 1 and 0 pattern at 200 Mb/s, 20% to 80% of VOD 6
Differential Low to High Propagation Delay tPLHD 1 2.5 ns Alternating 1 and 0 pattern at 200 Mb/s, 50% VOD input to output 6
Differential High to Low Propagation Delay tPHLD 1 2.5 ns Alternating 1 and 0 pattern at 200 Mb/s, 50% VOD input to output 6
Pulse Skew tSKD1 25 75 ps /tPLHD-tPHLD/ 6
Output Channel to Channel Skew tSKCC 50 115 ps Difference in propagation delay among all output channels 6
Jitter RJ (0% Pre-emphasis) tJIT 1.1 1.5 psrms RJ - Alternating 1 and 0 at 750MHz 7
Jitter DJ (0% Pre-emphasis) tJIT 20 34 psp-p DJ - K28.5 Pattern, 1.5 Gbps 7
Jitter TJ (0% Pre-emphasis) tJIT 14 28 psp-p TJ - PRBS 2^7-1 Pattern, 1.5 Gbps 7
LVDS Output Enable Time tON 0.5 1.5 µs ENA_n, ENB_n, or ENL_n to OUT± change from TRI-STATE to active 7
LVDS Output Enable Time from Powerdown Mode tON2 10 20 µs ENA_n, ENB_n, or ENL_n to OUT± change from Powerdown Mode to active 7
LVDS Output Disable Time tOFF 12 ns ENA_n, ENB_n, or ENL_n to OUT± change from active to TRI-STATE or Powerdown mode 7
Input Capacitance (digital) CIN1 2 pF Any Digital Input Pin to VSS 6
Output Capacitance (digital) COUT1 4 pF Any Digital Output Pin to VSS 6
Input Capacitance (LVDS) CIN2 2 pF IN+ or IN- to VSS 6
Output Capacitance (LVDS) COUT2 4 pF OUT+ or OUT- to GND when TRI-STATE 6

CAD (KiCad official)

  • Symbol: DS15MB200TSQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds15mb200tsq-etched.step / ds15mb200tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds15mb200tsq.step / ds15mb200tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 5af4c72a7d27eccb, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF