component
DS1302ZN
Public Made by Adomby adom
HGSEMI Real Time Clocks, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9d ago |
| viewers | 9d ago |
| ds1302zn-etched.glb | 9d ago |
| ds1302zn-etched.step | 9d ago |
| ds1302zn-hero.glb | 9d ago |
| ds1302zn-hero.overlay.json | 9d ago |
| ds1302zn.glb | 9d ago |
| ds1302zn.kicad_mod | 9d ago |
| ds1302zn.kicad_sym | 9d ago |
| ds1302zn.lbr | 9d ago |
| ds1302zn.step | 9d ago |
| package.json | 9d ago |
| page.json | 9d ago |
| README.md | 9d ago |
DS1302ZN
HGSEMI · Real Time Clocks · DIP-8
DS1302ZN from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC2 | power_in | Main power supply input; the device runs from the higher of VCC1 or VCC2, and the recommended supply range is 2.0 V to 5.5 V. |
| 2 | X1 | passive | Connection to the 32.768 kHz crystal, which should have a specified load capacitance of 6 pF. |
| 3 | X2 | passive | Connection to the 32.768 kHz crystal, which should have a specified load capacitance of 6 pF. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | RST | input | Reset/chip-enable input: driving it high starts data transfer and driving it low aborts transfer and forces I/O to high impedance, and it must be low before VCC reaches 2.5 V at power-up. |
| 6 | I/O | bidirectional | Serial data input/output pin that goes high impedance when RST is low; at VCC=5 V the logic levels are TTL compatible. |
| 7 | SCLK | input | Serial clock input: data is sampled on rising edges and output on falling edges, and SCLK must be low when RST is driven high. |
| 8 | VCC1 | power_in | Backup power supply input that keeps the clock and RAM powered when VCC2 is absent, within the 2.0 V to 5.5 V recommended range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Clock/Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 引脚对地电压 (Voltage on any pin to ground) | VP | -0.5 | 7 | V | 3 | ||
| 工作温度 (Operating temperature, DS1302Z grade) | TA | -40 | 85 | ℃ | DS1302Z row (applies to DS1302ZN) | 3 | |
| 贮存温度 (Storage temperature) | TS | -55 | 125 | ℃ | 3 | ||
| 焊接温度 (Soldering temperature) | TH | 260 | ℃ | 10 s | 3 | ||
| 供给电源电压 (Supply voltage) | VCC1, VCC2 | 2 | 5.5 | V | TA=0℃～70℃ | 3 | |
| 逻辑1输入电压 (Logic 1 input voltage) | VIH | 2 | V | 3 | |||
| 逻辑0输入电压 (Logic 0 input voltage) | VIL | -0.3 | 0.3 | V | VCC=2.0V | 3 | |
| 逻辑0输入电压 (Logic 0 input voltage) | VIL | -0.3 | 0.8 | V | VCC=5V | 3 | |
| 输入电容 (Input capacitance) | CI | 10 | pF | TA=25℃ | 3 | ||
| I/O 电容 (I/O capacitance) | CI/O | 15 | pF | TA=25℃ | 3 | ||
| 晶体振荡器电容 (Crystal oscillator capacitance) | CX | 6 | pF | TA=25℃ | 3 | ||
| 输入电流 (Input current) | ILI | 500 | μA | 0℃至70℃; VCC=2.5V至5.5V | 4 | ||
| I/O 漏电流 (I/O leakage current) | ILO | 500 | μA | 0℃至70℃; VCC=2.5V至5.5V | 4 | ||
| 逻辑1输出电压 (Logic 1 output voltage) | VOH | 1.6 | V | VCC=2.5V | 4 | ||
| 逻辑1输出电压 (Logic 1 output voltage) | VOH | 2.4 | V | VCC=5V | 4 | ||
| 逻辑0输出电压 (Logic 0 output voltage) | VOL | 0.4 | V | VCC=2.5V | 4 | ||
| 供电电流 (Active supply current, VCC1) | ICC1A | 0.4 | mA | VCC1=2.5V | 4 | ||
| 供电电流 (Active supply current, VCC1) | ICC1A | 1.2 | mA | VCC1=5V | 4 | ||
| 时间保持电流 (Timekeeping current, VCC1) | ICC1T | 0.3 | μA | VCC1=2.5V | 4 | ||
| 时间保持电流 (Timekeeping current, VCC1) | ICC1T | 1 | μA | VCC1=5V | 4 | ||
| 静态电流 (Standby current, VCC1) | ICC1S | 100 | nA | VCC1=2.5V | 4 | ||
| 供电电流 (Active supply current, VCC2) | ICC2A | 0.425 | mA | VCC2=2.5V | 4 | ||
| 供电电流 (Active supply current, VCC2) | ICC2A | 1.28 | mA | VCC2=5V | 4 | ||
| 时间保持电流 (Timekeeping current, VCC2) | ICC2T | 25.3 | μA | VCC2=2.5V | 4 | ||
| 时间保持电流 (Timekeeping current, VCC2) | ICC2T | 81 | μA | VCC2=5V | 4 | ||
| 静态电流 (Standby current, VCC2) | ICC2S | 25 | μA | VCC2=2.5V | 4 | ||
| 静态电流 (Standby current, VCC2) | ICC2S | 80 | μA | VCC2=5V | 4 | ||
| CLK 到RST 保持 (CLK to RST hold) | tcch | 240 | ns | VCC=2V | 4 | ||
| CLK 到RST 保持 (CLK to RST hold) | tcch | 60 | ns | VCC=5V | 4 | ||
| RST 无效 (RST inactive time) | tcwh | 4 | ns | VCC=2V | 4 | ||
| RST 无效 (RST inactive time) | tcwh | 1 | ns | VCC=5V | 4 | ||
| RST 到I/O 高阻 (RST to I/O high-Z) | tcdz | 280 | ns | VCC=2V | 4 | ||
| RST 到I/O 高阻 (RST to I/O high-Z) | tcdz | 70 | ns | VCC=5V | 4 | ||
| SCLK 到I/O 高阻 (SCLK to I/O high-Z) | tccz | 280 | ns | VCC=2V | 4 | ||
| SCLK 到I/O 高阻 (SCLK to I/O high-Z) | tccz | 70 | ns | VCC=5V | 4 | ||
| Data 到CLK 建立 (Data to CLK setup) | tdc | 200 | ns | VCC=2V | 4 | ||
| Data 到CLK 建立 (Data to CLK setup) | tdc | 50 | ns | VCC=5V | 4 | ||
| CLK 到Data 保持 (CLK to Data hold) | tcdh | 280 | ns | VCC=2V | 4 | ||
| CLK 到Data 保持 (CLK to Data hold) | tcdh | 70 | ns | VCC=5V | 4 | ||
| CLK 到Data 延时 (CLK to Data delay) | tcdd | 800 | ns | VCC=2V | 4 | ||
| CLK 到Data 延时 (CLK to Data delay) | tcdd | 200 | ns | VCC=5V | 4 | ||
| CLK 低 (CLK low time) | tcl | 1000 | ns | VCC=2V | 4 | ||
| CLK 低 (CLK low time) | tcl | 250 | ns | VCC=5V | 4 | ||
| CLK 高 (CLK high time) | tch | 1000 | ns | VCC=2V | 4 | ||
| CLK 高 (CLK high time) | tch | 250 | ns | VCC=5V | 4 | ||
| CLK 频率 (CLK frequency) | tclk | 0.5 | MHz | VCC=2V | 5 | ||
| CLK 频率 (CLK frequency) | tclk | 2 | MHz | VCC=5V | 5 | ||
| CLK 上升和下降时间 (CLK rise and fall time) | tr, tf | 2000 | ns | VCC=2V | 5 | ||
| CLK 上升和下降时间 (CLK rise and fall time) | tr, tf | 500 | ns | VCC=5V | 5 | ||
| RST 到CLK 建立 (RST to CLK setup) | tCC | 4 | µs | VCC=2V | 5 | ||
| RST 到CLK 建立 (RST to CLK setup) | tCC | 1 | µs | VCC=5V | 5 | ||
| 涓流充电电阻 R1 (Trickle-charge resistor R1) | R1 | 2 | kΩ | 4 | |||
| 涓流充电电阻 R2 (Trickle-charge resistor R2) | R2 | 4 | kΩ | 4 | |||
| 涓流充电电阻 R3 (Trickle-charge resistor R3) | R3 | 8 | kΩ | 4 | |||
| 涓流充电二极管压降 (Trickle-charge diode forward drop) | VTD | 0.7 | V | 4 |
CAD (KiCad official)
- Symbol:
DS1302ZN - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
ds1302zn-etched.step/ds1302zn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds1302zn.step/ds1302zn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (15 pp, sha256
610b1880d250ea8d, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).