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DS1302ZMM

Public Made by Adom

by adom

HGSEMI Real Time Clocks, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS1302ZMM

HGSEMI · Real Time Clocks · MSOP-8

DS1302ZMM from HGSEMI, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC2 power_in Primary supply pin for dual-supply systems; the DS1302 runs from whichever of VCC1 or VCC2 is higher, and VCC2 is specified at 2.0 V to 5.5 V.
2 X1 passive Connects to one terminal of the 32.768 kHz crystal, which should present a 6 pF load capacitance.
3 X2 passive Connects to the other terminal of the 32.768 kHz crystal, which should present a 6 pF load capacitance.
4 GND power_in Ground reference for the device.
5 RST input Reset/enable input: driving it high starts a data transfer, driving it low terminates the transfer and puts I/O in high impedance, and it must be low before VCC reaches 2.5 V at power-up.
6 I/O bidirectional Serial data input/output; input data is valid on SCLK rising edges, output data changes on SCLK falling edges, and the pin goes high-impedance when RST is low.
7 SCLK input Serial clock input that synchronizes all data transfers, and it must be low when RST is driven high.
8 VCC1 power_in Backup supply pin for battery or super-capacitor backup of the clock and RAM; the DS1302 runs from whichever of VCC1 or VCC2 is higher, and VCC1 is specified at 2.0 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package MSOP-8
Category Clock/Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC1，VCC2 2 5.5 V 3
Logic 1 input voltage VIH 2 V 3
Logic 0 input voltage VIL -0.3 0.3 V VCC=2.0V 3
Logic 0 input voltage VIL -0.3 0.8 V VCC=5V 3
Input capacitance CI 10 pF 3
I/O capacitance CI/O 15 pF 3
Crystal oscillator capacitance CX 6 pF 3
Input current ILI 500 μA 4
I/O leakage current ILO 500 μA 4
Logic 1 output voltage VOH 1.6 V VCC=2.5V 4
Logic 1 output voltage VOH 2.4 V VCC=5V 4
Logic 0 output voltage VOL 0.4 V VCC=2.5V 4
Active supply current (VCC1) ICC1A 0.4 mA VCC1=2.5V 4
Active supply current (VCC1) ICC1A 1.2 mA VCC1=5V 4
Timekeeping current (VCC1) ICC1T 0.3 μA VCC1=2.5V 4
Timekeeping current (VCC1) ICC1T 1 μA VCC1=5V 4
Static current (VCC1) ICC1S 100 nA VCC1=2.5V 4
Active supply current (VCC2) ICC2A 0.425 mA VCC2=2.5V 4
Active supply current (VCC2) ICC2A 1.28 mA VCC2=5V 4
Timekeeping current (VCC2) ICC2T 25.3 μA VCC2=2.5V 4
Timekeeping current (VCC2) ICC2T 81 μA VCC2=5V 4
Static current (VCC2) ICC2S 25 μA VCC2=2.5V 4
Static current (VCC2) ICC2S 80 μA VCC2=5V 4
CLK to RST hold time tcch 240 ns VCC=2V 4
CLK to RST hold time tcch 60 ns VCC=5V 4
RST inactive time tcwh 4 ns VCC=2V 4
RST inactive time tcwh 1 ns VCC=5V 4
RST to I/O high-Z tcdz 280 ns VCC=2V 4
RST to I/O high-Z tcdz 70 ns VCC=5V 4
SCLK to I/O high-Z tccz 280 ns VCC=2V 4
SCLK to I/O high-Z tccz 70 ns VCC=5V 4
Data to CLK setup time tdc 200 ns VCC=2V 4
Data to CLK setup time tdc 50 ns VCC=5V 4
CLK to Data hold time tcdh 280 ns VCC=2V 4
CLK to Data hold time tcdh 70 ns VCC=5V 4
CLK to Data delay tcdd 800 ns VCC=2V 4
CLK to Data delay tcdd 200 ns VCC=5V 4
CLK low time tcl 1000 ns VCC=2V 4
CLK low time tcl 250 ns VCC=5V 4
CLK high time tch 1000 ns VCC=2V 4
CLK high time tch 250 ns VCC=5V 4
CLK frequency tclk 0.5 MHz VCC=2V 5
CLK frequency tclk 2 MHz VCC=5V 5
CLK rise and fall time tr，tf 2000 ns VCC=2V 5
CLK rise and fall time tr，tf 500 ns VCC=5V 5
RST to CLK setup time tCC 4 µs VCC=2V 5
RST to CLK setup time tCC 1 µs VCC=5V 5
Voltage on any pin to ground VP -0.5 7 V 3
Operating temperature (DS1302Z) TA -40 85 ℃ DS1302Z 3
Storage temperature TS -55 125 ℃ 3
Soldering temperature TH 260 ℃ 10 s 3
Trickle charge resistor R1 R1 2 kΩ 4
Trickle charge resistor R2 R2 4 kΩ 4
Trickle charge resistor R3 R3 8 kΩ 4
Trickle charge diode forward voltage drop VTD 0.7 V 4

CAD (KiCad official)

  • Symbol: DS1302ZMM
  • Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
  • 3D model: MSOP-8 (KiCad packages3D, STEP)
  • 3D model files: ds1302zmm-etched.step / ds1302zmm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds1302zmm.step / ds1302zmm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (15 pp, sha256 610b1880d250ea8d, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF