component
DS1302IDRG
Public Made by Adomby adom
HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
ds1302idrg: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
a2fc212
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{
"schema_version": 1,
"type": "component",
"slug": "ds1302idrg",
"title": "DS1302IDRG",
"brief": "HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"rtc",
"ds1302idrg"
],
"component": {
"mpn": "DS1302IDRG",
"manufacturer": "HANSCHIP semiconductor",
"package": "SOP-8",
"pin_count": 8,
"category": "RTC",
"subcategory": "Real-time Clocks (RTC)",
"datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2204251600_HANSCHIP-semiconductor-DS1302IDRG_C2977121.pdf",
"parts": {
"symbol": "ds1302idrg.kicad_sym",
"footprint": "ds1302idrg.kicad_mod",
"model_3d": "ds1302idrg-etched.glb",
"model_3d_plain": "ds1302idrg.glb",
"model_3d_step": "ds1302idrg-etched.step",
"model_3d_step_plain": "ds1302idrg.step",
"lbr": "ds1302idrg.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "VCC2",
"type": "power_in",
"description": "Primary power supply input (main supply). Operating range 2.0 V to 5.5 V. Feeds the trickle-charge circuit that can charge a backup cell/cap on VCC1."
},
{
"number": "2",
"name": "X1",
"type": "passive",
"description": "Connection for a 32.768 kHz crystal oscillator (one terminal). Recommended crystal load capacitance CX = 6 pF typical."
},
{
"number": "3",
"name": "X2",
"type": "passive",
"description": "Connection for a 32.768 kHz crystal oscillator (other terminal). Pair with X1 across the crystal; CX ≈ 6 pF."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Device ground reference (0 V)."
},
{
"number": "5",
"name": "RST",
"type": "input",
"description": "Reset / chip enable input, active high. Drive high to initiate a data transfer; drive low to terminate a transfer and place I/O into a high-impedance state. Must be low at power-up until VCC ≥ 2.5 V; when driving RST high, SCLK must be at logic 0."
},
{
"number": "6",
"name": "I/O",
"type": "bidirectional",
"description": "Serial data input/output for the 3-wire interface. Command/data bits are clocked in on rising SCLK edges and read data is clocked out on falling SCLK edges. Goes high-impedance when RST is low. TTL-compatible at VCC = 5 V."
},
{
"number": "7",
"name": "SCLK",
"type": "input",
"description": "Serial clock input for the 3-wire interface. Synchronizes shifting of command and data bytes on the I/O pin. Maximum clock rate 0.5 MHz at VCC = 2.5 V, 2.0 MHz at VCC = 5 V."
},
{
"number": "8",
"name": "VCC1",
"type": "power_in",
"description": "Backup power supply input (typically a Ni-Cd cell or supercap). Powers the RTC and RAM when VCC2 is absent; can be trickle-charged from VCC2 through selectable diode/resistor combinations (R1=2 kΩ, R2=4 kΩ, R3=8 kΩ; VTD ≈ 0.7 V)."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2204251600_HANSCHIP-semiconductor-DS1302IDRG_C2977121.pdf",
"pages": 15,
"sha256": "6dfca75d1e1627dd",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ds1302idrg.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ds1302idrg-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "7d5917c6c7181480b0b800266299edcbefe91c5fcb0ce75d1d78e521ab2babb8",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "HANSCHIP semiconductor",
"Package": "SOP-8",
"Category": "RTC",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"ds1302idrg"
],
"discovery_pitch": "DS1302IDRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ds1302idrg.kicad_sym",
"ds1302idrg.kicad_mod",
"ds1302idrg.glb",
"ds1302idrg.step",
"ds1302idrg-etched.step",
"ds1302idrg.lbr",
"docs/hero.png",
"docs/ds1302idrg-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "DS1302CDRG",
"kind": "unknown"
},
{
"mpn": "DS1302IDRG",
"kind": "packaging"
},
{
"mpn": "DS1302CDRG4",
"kind": "unknown"
},
{
"mpn": "DS1302IDRG4",
"kind": "packaging"
},
{
"mpn": "DS1302CPG",
"kind": "unknown"
},
{
"mpn": "DS1302IPG",
"kind": "unknown"
},
{
"mpn": "DS1302CDGKRG",
"kind": "unknown"
},
{
"mpn": "DS1302IDGKRG",
"kind": "unknown"
}
],
"updated_at": "2026-09-24T20:04:17.065Z"
}