DS1302CDRG

{
  "schema_version": 1,
  "type": "component",
  "slug": "ds1302cdrg",
  "title": "DS1302CDRG",
  "brief": "HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "rtc",
    "ds1302cdrg"
  ],
  "component": {
    "mpn": "DS1302CDRG",
    "manufacturer": "HANSCHIP semiconductor",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "RTC",
    "subcategory": "Real-time Clocks (RTC)",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2212011600_HANSCHIP-semiconductor-DS1302CDRG_C5145438.pdf",
    "parts": {
      "symbol": "ds1302cdrg.kicad_sym",
      "footprint": "ds1302cdrg.kicad_mod",
      "model_3d": "ds1302cdrg-etched.glb",
      "model_3d_plain": "ds1302cdrg.glb",
      "model_3d_step": "ds1302cdrg-etched.step",
      "model_3d_step_plain": "ds1302cdrg.step",
      "lbr": "ds1302cdrg.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VCC2",
        "type": "power_in",
        "description": "Primary (main) power supply input, 2.0 V to 5.5 V. When VCC2 > VCC1 + 0.2 V, the device is powered from VCC2 and can source the trickle charger to VCC1."
      },
      {
        "number": "2",
        "name": "X1",
        "type": "passive",
        "description": "Connection for a 32.768 kHz quartz crystal. Internal oscillator load capacitance is ~6 pF; external crystal typically 6 pF CL."
      },
      {
        "number": "3",
        "name": "X2",
        "type": "passive",
        "description": "Connection for the other terminal of the 32.768 kHz quartz crystal. Pairs with X1 to form the timekeeping oscillator."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference (0 V)."
      },
      {
        "number": "5",
        "name": "RST",
        "type": "input",
        "description": "Active-high reset / chip-enable input. Must be driven high to initiate any data transfer; while low all transfers are terminated and I/O goes high-impedance. TTL compatible at VCC=5 V."
      },
      {
        "number": "6",
        "name": "I/O",
        "type": "bidirectional",
        "description": "Bidirectional serial data pin for the 3-wire interface. Command/data bytes are clocked in on SCLK rising edges (LSB first) and read data is driven on SCLK falling edges. Tri-stated when RST is low or between bit phases."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input for the 3-wire bus. Max 2.0 MHz at VCC=5 V, 0.5 MHz at VCC=2.5 V. Must be low when RST is driven high."
      },
      {
        "number": "8",
        "name": "VCC1",
        "type": "power_in",
        "description": "Backup power supply input (typically a battery or super-cap). Powers the RTC when VCC2 falls below VCC1; also the sink node of the optional on-chip trickle charger from VCC2."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2212011600_HANSCHIP-semiconductor-DS1302CDRG_C5145438.pdf",
        "pages": 15,
        "sha256": "6dfca75d1e1627dd",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "ds1302cdrg.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ds1302cdrg-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
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        "sha256": "7b4498a10ac8dab3de16139a5724c4ee08676f51d314b56c241fdf2d95f64a62",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HANSCHIP semiconductor",
      "Package": "SOP-8",
      "Category": "RTC",
      "Pins": "8"
    }
  },
  "sections": [
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    "readme",
    "breadcrumbs",
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  "discovery_triggers": [
    "ds1302cdrg"
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  "discovery_pitch": "DS1302CDRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "ds1302cdrg.kicad_sym",
    "ds1302cdrg.kicad_mod",
    "ds1302cdrg.glb",
    "ds1302cdrg.step",
    "ds1302cdrg-etched.step",
    "ds1302cdrg.lbr",
    "docs/hero.png",
    "docs/ds1302cdrg-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "DS1302CDRG",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGIDRG",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRG4",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGIDRG4",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGCPG",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGIPG",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGCDGKRG",
      "kind": "packaging"
    },
    {
      "mpn": "DS1302CDRGIDGKRG",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T20:04:00.189Z"
}