component
DS1302CDRG
Public Made by Adomby adom
HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ds1302cdrg",+ "title": "DS1302CDRG",+ "brief": "HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "rtc", "ds1302cdrg" ],+ "component": {+ "mpn": "DS1302CDRG",+ "manufacturer": "HANSCHIP semiconductor",+ "package": "SOP-8",+ "pin_count": 8,+ "category": "RTC",+ "subcategory": "Real-time Clocks (RTC)",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2212011600_HANSCHIP-semiconductor-DS1302CDRG_C5145438.pdf",+ "parts": {+ "symbol": "ds1302cdrg.kicad_sym",+ "footprint": "ds1302cdrg.kicad_mod",+ "model_3d": "ds1302cdrg.glb",+ "model_3d_step": "ds1302cdrg.step",+ "lbr": "ds1302cdrg.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "VCC2",+ "type": "power_in",+ "description": "Primary (main) power supply input, 2.0 V to 5.5 V. When VCC2 > VCC1 + 0.2 V, the device is powered from VCC2 and can source the trickle charger to VCC1."+ },+ {+ "number": "2",+ "name": "X1",+ "type": "passive",+ "description": "Connection for a 32.768 kHz quartz crystal. Internal oscillator load capacitance is ~6 pF; external crystal typically 6 pF CL."+ },+ {+ "number": "3",+ "name": "X2",+ "type": "passive",+ "description": "Connection for the other terminal of the 32.768 kHz quartz crystal. Pairs with X1 to form the timekeeping oscillator."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground reference (0 V)."+ },+ {+ "number": "5",+ "name": "RST",+ "type": "input",+ "description": "Active-high reset / chip-enable input. Must be driven high to initiate any data transfer; while low all transfers are terminated and I/O goes high-impedance. TTL compatible at VCC=5 V."+ },+ {+ "number": "6",+ "name": "I/O",+ "type": "bidirectional",+ "description": "Bidirectional serial data pin for the 3-wire interface. Command/data bytes are clocked in on SCLK rising edges (LSB first) and read data is driven on SCLK falling edges. Tri-stated when RST is low or between bit phases."+ },+ {+ "number": "7",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input for the 3-wire bus. Max 2.0 MHz at VCC=5 V, 0.5 MHz at VCC=2.5 V. Must be low when RST is driven high."+ },+ {+ "number": "8",+ "name": "VCC1",+ "type": "power_in",+ "description": "Backup power supply input (typically a battery or super-cap). Powers the RTC when VCC2 falls below VCC1; also the sink node of the optional on-chip trickle charger from VCC2."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2212011600_HANSCHIP-semiconductor-DS1302CDRG_C5145438.pdf",+ "pages": 15,+ "sha256": "6dfca75d1e1627dd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "HANSCHIP semiconductor",+ "Package": "SOP-8",+ "Category": "RTC",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ds1302cdrg"+ ],+ "discovery_pitch": "DS1302CDRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/ds1302cdrg-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }