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DS125DF111SQE
Public Made by Adomby adom
Texas Instruments Interface - Specialized, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# DS125DF111SQE++**Texas Instruments** · Interface - Specialized · WQFN-24-EP(4x4)++DS125DF111SQE from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LPF_REF_A | bidirectional | Loop filter connection for channel A; a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A. |+| 2 | LPF_CP_A | bidirectional | Loop filter connection for channel A; a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A. |+| 3 | ENSMB | input | 4-level SMBus enable: HIGH selects register access (SMBus slave mode), FLOAT selects SMBus master read from external EEPROM, 20K to GND is reserved, and LOW selects external pin control mode. |+| 4 | SDA/DEMA | bidirectional | SMBus data input/open-drain output that requires an external pull-up resistor and is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH A output de-emphasis level. |+| 5 | SCL/DEMB | bidirectional | SMBus clock input in slave mode (open-drain output in master mode) that is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH B output de-emphasis level. |+| 6 | TX_DIS/LPBK | input | 4-level input that disables the OUTB transmitter when HIGH (OUTA enabled, OUTB disabled) and enables OUTA/OUTB when LOW; in pin control mode it selects the loopback routing. |+| 7 | OUTA+ | output | Non-inverting CML-compatible differential output for channel A that requires AC coupling. |+| 8 | OUTA- | output | Inverting CML-compatible differential output for channel A that requires AC coupling. |+| 9 | VODA/READEN# | input | LVCMOS input that initiates an SMBus master EEPROM read when pulled low and must be tied to logic 0 in SMBus slave mode; in pin control mode it sets the CH A output launch amplitude. |+| 10 | ADDR1/VODB/DONE# | bidirectional | LVCMOS pin that sets the SMBus address bit 1 in slave mode, drives DONE# low when the SMBus master EEPROM read completes (VOH referenced to VIN), and sets the CH B output launch amplitude in pin control mode. |+| 11 | INB+ | input | Non-inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |+| 12 | INB- | input | Inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |+| 13 | LOS/INT# | output | Open-drain output that is driven LOW when a valid signal is present on INA and released on loss of signal, requiring an external pull-up (typically 2.5 V or 3.3 V); it can be redefined as INT#. |+| 14 | REFCLK_IN | input | LVCMOS reference clock input that requires a 25 MHz ±100 ppm clock from an external oscillator. |+| 15 | VIN | power_in | Regulator input with integrated supply mode control: 3.3 V ±10% in 3.3-V supply mode, or 2.5 V ±5% in 2.5-V mode where it connects directly to the VDD pins. |+| 16 | ADDR0/LOCK | bidirectional | Strap input read at power-up that sets the SMBus address and changes the LOCK output definition; LOCK is an LVCMOS output with VOH referenced to VIN. |+| 17 | LPF_CP_B | bidirectional | Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B. |+| 18 | LPF_REF_B | bidirectional | Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B. |+| 19 | OUTB- | output | Inverting CML-compatible differential output for channel B that requires AC coupling. |+| 20 | OUTB+ | output | Non-inverting CML-compatible differential output for channel B that requires AC coupling. |+| 21 | VDD | power_in | 2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input. |+| 22 | VDD | power_in | 2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input. |+| 23 | INA- | input | Inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |+| 24 | INA+ | input | Non-inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |+| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-24-EP(4x4) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `DS125DF111SQE`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `ds125df111sqe-etched.step` / `ds125df111sqe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds125df111sqe.step` / `ds125df111sqe.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds125df111) (56 pp, sha256 `8e3182cf3cd5933c`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds125df111sqe-datasheet.pdf)
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a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A."+ },+ {+ "number": "2",+ "name": "LPF_CP_A",+ "type": "bidirectional",+ "description": "Loop filter connection for channel A; a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A."+ },+ {+ "number": "3",+ "name": "ENSMB",+ "type": "input",+ "description": "4-level SMBus enable: HIGH selects register access (SMBus slave mode), FLOAT selects SMBus master read from external EEPROM, 20K to GND is reserved, and LOW selects external pin control mode."+ },+ {+ "number": "4",+ "name": "SDA/DEMA",+ "type": "bidirectional",+ "description": "SMBus data input/open-drain output that requires an external pull-up resistor and is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH A output de-emphasis level."+ },+ {+ "number": "5",+ "name": "SCL/DEMB",+ "type": "bidirectional",+ "description": "SMBus clock input in slave mode (open-drain output in master mode) that is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH B output de-emphasis level."+ },+ {+ "number": "6",+ "name": "TX_DIS/LPBK",+ "type": "input",+ "description": "4-level input that disables the OUTB transmitter when HIGH (OUTA enabled, OUTB disabled) and enables OUTA/OUTB when LOW; in pin control mode it selects the loopback routing."+ },+ {+ "number": "7",+ "name": "OUTA+",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output for channel A that requires AC coupling."+ },+ {+ "number": "8",+ "name": "OUTA-",+ "type": "output",+ "description": "Inverting CML-compatible differential output for channel A that requires AC coupling."+ },+ {+ "number": "9",+ "name": "VODA/READEN#",+ "type": "input",+ "description": "LVCMOS input that initiates an SMBus master EEPROM read when pulled low and must be tied to logic 0 in SMBus slave mode; in pin control mode it sets the CH A output launch amplitude."+ },+ {+ "number": "10",+ "name": "ADDR1/VODB/DONE#",+ "type": "bidirectional",+ "description": "LVCMOS pin that sets the SMBus address bit 1 in slave mode, drives DONE# low when the SMBus master EEPROM read completes (VOH referenced to VIN), and sets the CH B output launch amplitude in pin control mode."+ },+ {+ "number": "11",+ "name": "INB+",+ "type": "input",+ "description": "Non-inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI."+ },+ {+ "number": "12",+ "name": "INB-",+ "type": "input",+ "description": "Inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI."+ },+ {+ "number": "13",+ "name": "LOS/INT#",+ "type": "output",+ "description": "Open-drain output that is driven LOW when a valid signal is present on INA and released on loss of signal, requiring an external pull-up (typically 2.5 V or 3.3 V); it can be redefined as INT#."+ },+ {+ "number": "14",+ "name": "REFCLK_IN",+ "type": "input",+ "description": "LVCMOS reference clock input that requires a 25 MHz ±100 ppm clock from an external oscillator."+ },+ {+ "number": "15",+ "name": "VIN",+ "type": "power_in",+ "description": "Regulator input with integrated supply mode control: 3.3 V ±10% in 3.3-V supply mode, or 2.5 V ±5% in 2.5-V mode where it connects directly to the VDD pins."+ },+ {+ "number": "16",+ "name": "ADDR0/LOCK",+ "type": "bidirectional",+ "description": "Strap input read at power-up that sets the SMBus address and changes the LOCK output definition; LOCK is an LVCMOS output with VOH referenced to VIN."+ },+ {+ "number": "17",+ "name": "LPF_CP_B",+ "type": "bidirectional",+ "description": "Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B."+ },+ {+ "number": "18",+ "name": "LPF_REF_B",+ "type": "bidirectional",+ "description": "Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B."+ },+ {+ "number": "19",+ "name": "OUTB-",+ "type": "output",+ "description": "Inverting CML-compatible differential output for channel B that requires AC coupling."+ },+ {+ "number": "20",+ "name": "OUTB+",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output for channel B that requires AC coupling."+ },+ {+ "number": "21",+ "name": "VDD",+ "type": "power_in",+ "description": "2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input."+ },+ {+ "number": "22",+ "name": "VDD",+ "type": "power_in",+ "description": "2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input."+ },+ {+ "number": "23",+ "name": "INA-",+ "type": "input",+ "description": "Inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI."+ },+ {+ "number": "24",+ "name": "INA+",+ "type": "input",+ "description": "Non-inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI."+ },+ {+ "number": "25",+ "name": "DAP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed pad is listed in the datasheet as DAP (GND reference) but has no printed numeric pin num; The datasheet lists the differential pairs as OUTA±/OUTB±/INA±/INB± with pin numbers (e.g., OUTA± 7,; ADDR0/LOCK is listed as an input strap (pin table) and as an LVCMOS output (LOCK function); typed as",+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 15,+ "cost_usd": 0.1201,+ "at": "2026-10-08T01:36:55"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds125df111",+ "pages": 56,+ "sha256": "8e3182cf3cd5933c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds125df111sqe.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds125df111sqe-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c088fa46af1046913c4777bcc3f640ce14d920eaa543a9ad436ea224dda75ccd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}