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DS125DF111SQE
Public Made by Adomby adom
Texas Instruments Interface - Specialized, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS125DF111SQE
Texas Instruments · Interface - Specialized · WQFN-24-EP(4x4)
DS125DF111SQE from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LPF_REF_A | bidirectional | Loop filter connection for channel A; a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A. |
| 2 | LPF_CP_A | bidirectional | Loop filter connection for channel A; a 22 nF ±10% capacitor is placed in series between LPF_CP_A and LPF_REF_A. |
| 3 | ENSMB | input | 4-level SMBus enable: HIGH selects register access (SMBus slave mode), FLOAT selects SMBus master read from external EEPROM, 20K to GND is reserved, and LOW selects external pin control mode. |
| 4 | SDA/DEMA | bidirectional | SMBus data input/open-drain output that requires an external pull-up resistor and is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH A output de-emphasis level. |
| 5 | SCL/DEMB | bidirectional | SMBus clock input in slave mode (open-drain output in master mode) that is 3.3 V LVCMOS tolerant; in pin control mode it sets the CH B output de-emphasis level. |
| 6 | TX_DIS/LPBK | input | 4-level input that disables the OUTB transmitter when HIGH (OUTA enabled, OUTB disabled) and enables OUTA/OUTB when LOW; in pin control mode it selects the loopback routing. |
| 7 | OUTA+ | output | Non-inverting CML-compatible differential output for channel A that requires AC coupling. |
| 8 | OUTA- | output | Inverting CML-compatible differential output for channel A that requires AC coupling. |
| 9 | VODA/READEN# | input | LVCMOS input that initiates an SMBus master EEPROM read when pulled low and must be tied to logic 0 in SMBus slave mode; in pin control mode it sets the CH A output launch amplitude. |
| 10 | ADDR1/VODB/DONE# | bidirectional | LVCMOS pin that sets the SMBus address bit 1 in slave mode, drives DONE# low when the SMBus master EEPROM read completes (VOH referenced to VIN), and sets the CH B output launch amplitude in pin control mode. |
| 11 | INB+ | input | Non-inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |
| 12 | INB- | input | Inverting CML differential input for channel B with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |
| 13 | LOS/INT# | output | Open-drain output that is driven LOW when a valid signal is present on INA and released on loss of signal, requiring an external pull-up (typically 2.5 V or 3.3 V); it can be redefined as INT#. |
| 14 | REFCLK_IN | input | LVCMOS reference clock input that requires a 25 MHz ±100 ppm clock from an external oscillator. |
| 15 | VIN | power_in | Regulator input with integrated supply mode control: 3.3 V ±10% in 3.3-V supply mode, or 2.5 V ±5% in 2.5-V mode where it connects directly to the VDD pins. |
| 16 | ADDR0/LOCK | bidirectional | Strap input read at power-up that sets the SMBus address and changes the LOCK output definition; LOCK is an LVCMOS output with VOH referenced to VIN. |
| 17 | LPF_CP_B | bidirectional | Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B. |
| 18 | LPF_REF_B | bidirectional | Loop filter connection for channel B; a 22 nF ±10% capacitor is placed in series between LPF_CP_B and LPF_REF_B. |
| 19 | OUTB- | output | Inverting CML-compatible differential output for channel B that requires AC coupling. |
| 20 | OUTB+ | output | Non-inverting CML-compatible differential output for channel B that requires AC coupling. |
| 21 | VDD | power_in | 2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input. |
| 22 | VDD | power_in | 2.5 V ±5% supply pin; in 3.3-V supply mode it is fed by the internal output regulator and needs only decoupling, while in 2.5-V supply mode it is a 2.5 V ±5% input. |
| 23 | INA- | input | Inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |
| 24 | INA+ | input | Non-inverting CML differential input for channel A with an on-chip 100 Ω terminating resistor; inputs require AC coupling, with 100 nF capacitors recommended by TI. |
| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x4) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
DS125DF111SQE - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
ds125df111sqe-etched.step/ds125df111sqe-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds125df111sqe.step/ds125df111sqe.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (56 pp, sha256
8e3182cf3cd5933c, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).