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DS125BR111RTWT

Public Made by Adom

by adom

Texas Instruments Signal Buffers, Repeaters, Splitters, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS125BR111RTWT

Texas Instruments · Signal Buffers, Repeaters, Splitters · WQFN-24(4x4)

DS125BR111RTWT from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AD3/EQB0 input In pin mode this 4-level input sets the channel B equalization level (EQB0), and in SMBus mode it is SMBus slave address input AD3; EQB0 is defined only when ENSMB is low.
2 AD2/EQB1 input In pin mode this input is EQB1, which the datasheet states is not used in this design and should be tied to GND; in SMBus mode it is SMBus slave address input AD2.
3 ENSMB input 4-level input that selects SMBus register access when tied 1 kΩ to VDD, read of external EEPROM when floating, and pin mode when tied 1 kΩ to GND.
4 SDA/VODA_DB bidirectional SMBus bidirectional open-drain data pin requiring external pull-up of typically 2 kΩ to 5 kΩ and 3.3 V tolerance in SMBus mode; in pin mode it is VODA_DB, which should be held Low for SAS and PCIe applications.
5 SCL/VODB_DB bidirectional SMBus clock input (slave mode) or open-drain clock output while loading EEPROM (master mode); in pin mode it is VODB_DB, which should be held Low for SAS and PCIe applications.
6 PWDN input LVCMOS power-down input where tying High selects low power/power down and tying GND selects normal operation.
7 OUTA+ output Non-inverting 50 Ω CML driver output for channel A, compatible with AC-coupled CML inputs and requiring AC coupling.
8 OUTA- output Inverting 50 Ω CML driver output for channel A, compatible with AC-coupled CML inputs and requiring AC coupling.
9 AD1/EQA1 input In pin mode this input is EQA1, which the datasheet states is not used in this design and should be tied to GND; in SMBus mode it is SMBus slave address input AD1.
10 AD0/EQA0 input In pin mode this 4-level input sets the channel A equalization level (EQA0), and in SMBus mode it is SMBus slave address input AD0; EQA0 is defined only when ENSMB is low.
11 INB+ input Non-inverting CML differential input to the equalizer with an on-chip 50 Ω termination to VDD when enabled by RXDET logic; AC coupling is required.
12 INB- input Inverting CML differential input to the equalizer with an on-chip 50 Ω termination to VDD when enabled by RXDET logic; AC coupling is required.
13 RES unconnected Reserved pin that the datasheet states must be left floating.
14 SD_TH input 4-level input setting the internal signal detect threshold for system debug only, which does not control the high-speed datapath.
15 VIN power_in Supply input that must be fed 3.3 V in 3.3 V mode and left floating in 2.5 V mode.
16 VDD_SEL input Internal regulator control: float selects 2.5 V mode, tie to GND selects 3.3 V mode (enables internal regulator).
17 READEN/VOD_SEL input In SMBus slave mode this pin must be tied Low for AD[3:0] to be active (High or float gives address 0xB0); in pin mode it is VOD_SEL, a 4-level input controlling the low-frequency input-to-output voltage amplitude ratio.
18 DONE/RXDET bidirectional DONE is a valid register load status output (High means EEPROM load failed or incomplete, Low means passed) when ENSMB floats; RXDET in pin mode enables a 50 Ω or >50 kΩ termination to the power rail depending on input level.
19 OUTB- output Inverting 50 Ω CML driver output for channel B, compatible with AC-coupled CML inputs and requiring AC coupling.
20 OUTB+ output Non-inverting 50 Ω CML driver output for channel B, compatible with AC-coupled CML inputs and requiring AC coupling.
21 VDD power_in Supply pin for CML/analog circuitry; connect to 2.5 V in 2.5 V mode and decouple to GND with 0.22 µF capacitance in 3.3 V mode.
22 VDD power_in Supply pin for CML/analog circuitry; connect to 2.5 V in 2.5 V mode and decouple to GND with 0.22 µF capacitance in 3.3 V mode.
23 INA- input Inverting CML differential input to the equalizer with an on-chip 50 Ω termination to VDD when enabled by RXDET logic; AC coupling is required.
24 INA+ input Non-inverting CML differential input to the equalizer with an on-chip 50 Ω termination to VDD when enabled by RXDET logic; AC coupling is required.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24(4x4)
Category Communication Interface Chip/UART/485/232
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD - 2.5 V) -0.5 2.75 V 6
Supply Voltage (VIN - 3.3 V) -0.5 4 V 6
LVCMOS Input/Output Voltage -0.5 4 V 6
CML Input Current -30 30 mA 6
Storage temperature range Tstg -40 125 °C 6
Lead Temperature Range Soldering Tsolder 260 °C 4 sec. 6
Electrostatic discharge, human body model V(ESD) -5000 5000 V HBM, all pins 6
Electrostatic discharge, charged device model V(ESD) -1250 1250 V CDM, all pins 6
Supply Voltage (2.5 V mode) 2.375 2.5 2.625 V 6
Supply Voltage (3.3 V mode) 3 3.3 3.6 V 6
Ambient Temperature -40 25 85 °C 6
Supply Noise up to 50 MHz 100 mVp-p allowed supply noise, typical conditions 6
Current Consumption IDD 40 60 mA VODx_DB = 0, EQ = 0, VOD_SEL = 1, RXDET = 1, PWDN = 0, VIN = 2.625 or 3.6 V 7
Power Down Current Consumption 7 13 mA PWDN = 1 7
Integrated LDO Regulator VDD VDD 2.375 2.5 2.625 V VIN = 3.0 - 3.6 V 7
High Level Input Voltage, 2.5 V Supply Mode Vih25 1.7 V 2.5 V Supply Mode; max printed as VDD 7
Low Level Input Voltage Vil 0 0.7 V 7
High Level Output Voltage (DONE pin) Voh 2 V Ioh = −4 mA 7
Low Level Output Voltage (DONE pin) Vol 0.4 V Iol = 4 mA 7
Input High Current (PWDN pin) Iih -15 15 µA VIN = 3.6 V, LVCMOS = 3.6 V 7
Input Low Current (PWDN pin) Iil -15 15 µA VIN = 3.6 V, LVCMOS = 0 V 7
Input High Current with internal resistors (4-level input pin) Iih 20 80 µA VIN = 3.6 V, LVCMOS = 3.6 V 7
Input Low Current with internal resistors (4-level input pin) Iil -160 -40 µA VIN = 3.6 V, LVCMOS = 0 V 7
RX Differential return loss SDD11 10 MHz RLRX-diff -19 dB SDD11 10 MHz 7
RX Differential return loss SDD11 2 GHz RLRX-diff -14 dB SDD11 2 GHz 7
RX Differential return loss SDD11 6-11.1 GHz RLRX-diff -8 dB SDD11 6-11.1 GHz 7
RX Common mode return loss RLRX-cm -10 dB 0.05 - 5 GHz 7
RX DC common mode impedance ZRX-dc 40 50 60 Ω Tested at VDD = 2.5 V 7
RX DC differential mode impedance ZRX-diff-dc 80 100 120 Ω Tested at VDD = 2.5 V 7
Transmitter rise/fall time TTX-RISE-FALL 40 ps 20% to 80% of differential output voltage 7
Transmitter rise/fall mismatch TRF-MISMATCH 0.01 UI 20% to 80% of differential output voltage 7
TX Differential return loss SDD22 10 MHz - 2 GHz RLTX-DIFF -15 dB SDD22 10 MHz - 2 GHz 8
TX Differential return loss SDD22 5.5 GHz RLTX-DIFF -12 dB SDD22 5.5 GHz 8
TX Differential return loss SDD22 11.1 GHz RLTX-DIFF -10 dB SDD22 11.1 GHz 8
TX Common mode return loss RLTX-CM -10 dB 0.05 - 5 GHz 8
DC differential TX impedance ZTX-DIFF-DC 100 Ω 8
Transmitter short circuit current limit ITX-SHORT 20 mA Total current, output shorted to VDD or GND 8
Absolute delta of DC common mode voltage during L0 and electrical idle VTX-CM-DC-ACTIVE-IDLE-DELTA 100 mV 8
Absolute delta of DC common mode voltage between TX+ and TX- VTX-CM-DC-LINE-DELTA 25 mV 8
Output Voltage Differential Swing (VOD = 001b, VID = 600 mVp-p) VTX-diff1-pp 440 500 550 mVp-p AC-coupled, terminated by 50 Ω to GND, VODx_DB = 0 dB, VID = 600 mVp-p, VOD = 001'b (0.7*VID) 8
Output Voltage Differential Swing (VOD = 001b, VID = 1000 mVp-p) VTX-diff2-pp 630 700 740 mVp-p AC-coupled, terminated by 50 Ω to GND, VODx_DB = 0 dB, VID = 1000 mVp-p, VOD = 001'b (0.7*VID) 8
Output Voltage Differential Swing (VOD = 111b, VID = 600 mVp-p) VTX-diff3-pp 570 650 740 mVp-p AC-coupled, terminated by 50 Ω to GND, VODx_DB = 0 dB, VID = 600 mVp-p, VOD = 111'b (1.05*VID) 8
Output Voltage Differential Swing (VOD = 111b, VID = 1000 mVp-p) VTX-diff4-pp 800 1010 1215 mVp-p AC-coupled, terminated by 50 Ω to GND, VODx_DB = 0 dB, VID = 1000 mVp-p, VOD = 111'b (1.05*VID) 8
Time to transition to valid differential signal after idle TTX-IDLE-DATA 0.04 ns VID = 1.0 Vp-p, 3 Gbps 8
Time to transition to idle after differential signal TTX-DATA-IDLE 0.7 ns VID = 1.0 Vp-p, 3 Gbps 8
Differential Propagation Delay TPD 70 ps EQ = Level 1 to Level 4 8
Residual Deterministic Jitter at 6 Gbps DJE1 0.06 UI VID = 0.8 Vp-p, PRBS15, EQ = 0x01, VOD = 111'b, VODx_DB = 0 dB 9
Residual Deterministic Jitter at 12 Gbps DJE2 0.12 UI VID = 0.8 Vp-p, PRBS15, EQ = 0x01, VOD = 111'b, VODx_DB = 0 dB 9
Additive Random Jitter (EVM only) RJADD1 300 fs RMS FR4, VID = 0.8 Vp-p, PRBS7, EQ = 0x00, VOD = 111'b, VODx_DB = 0 dB 9
Additive Random Jitter (10 in differential stripline) RJADD2 400 fs RMS 5 mil trace width, FR4, VID = 0.8 Vp-p, PRBS7, EQ = 0x03, VOD = 111'b, VODx_DB = 0 dB 9
Data, Clock Input Low Voltage VIL 0.8 V 10
Data, Clock Input High Voltage VIH 2.1 3.6 V 10
Output Low Voltage SDA or SCL VOL 0 0.36 V IOL = 1.25 mA 10
Nominal Bus Voltage VDD 2.375 3.6 V 10
Input Leakage Per Device pin (high) IIH-pin 20 150 µA Per Device pin 10
Input Leakage Per Device pin (low) IIL-pin -160 -40 µA Per Device pin 10
Capacitance for SDA and SCL CI 5 pF See (1)(2), typical value 10
Bus Operating Frequency (Slave Mode) FSMB 400 kHz ENSMB = VDD (Slave Mode) 10
Bus Operating Frequency (Master Mode) FSMB 280 400 520 kHz ENSMB = FLOAT (Master Mode) 10
SCL or SDA Fall Time tFALL 60 ns Read operation, RPU = 4.7 kΩ, Cb < 50 pF 10
SCL or SDA Rise Time tRISE 140 ns Read operation, RPU = 4.7 kΩ, Cb < 50 pF 10
Clock/Data Fall Time tF 300 ns Compliant to SMBus 2.0 10
Clock/Data Rise Time tR 1000 ns Compliant to SMBus 2.0 10
Junction-to-ambient thermal resistance RθJA 35 °C/W RTW 24 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 34 °C/W RTW 24 pins 6
Junction-to-board thermal resistance RθJB 13.4 °C/W RTW 24 pins 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.3 °C/W RTW 24 pins 6

CAD (KiCad official)

  • Symbol: DS125BR111RTWT
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: ds125br111rtwt-etched.step / ds125br111rtwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds125br111rtwt.step / ds125br111rtwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 0b7cee4cabe65671, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF