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DS125BR111RTWR

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Texas Instruments Signal Buffers, Repeaters, Splitters, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS125BR111RTWR

Texas Instruments · Signal Buffers, Repeaters, Splitters · WQFN-24-EP(4x4)

DS125BR111RTWR from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AD3/EQB0 input SMBus slave address input AD3 in SMBus mode, or EQB0 equalization level control for the B direction in Pin Mode (4-level LVCMOS).
2 AD2/EQB1 input SMBus slave address input AD2 in SMBus mode; as EQB1 in Pin Mode it is not used and must always be tied to GND.
3 ENSMB input 4-level SMBus enable: 1 kΩ to VDD = SMBus slave mode, float = read external EEPROM (master mode), 1 kΩ to GND = Pin Mode.
4 SDA/VODA_DB bidirectional SMBus bidirectional data pin (open drain output, needs external 2 kΩ to 5 kΩ pull-up, 3.3 V tolerant) in SMBus modes, or VODA_DB CHA output amplitude dynamic range control in Pin Mode (hold Low for SAS and PCIe).
5 SCL/VODB_DB bidirectional SMBus clock input in slave mode and clock output (open drain) when loading EEPROM in master mode, or VODB_DB CHB output amplitude control in Pin Mode (hold Low for SAS and PCIe).
6 PWDN input Power-down control: tie High = low power power-down, tie GND = normal operation.
7 OUTA+ output Non-inverting 50 Ω driver output of channel A, compatible with AC coupled CML inputs; AC coupling required.
8 OUTA- output Inverting 50 Ω driver output of channel A, compatible with AC coupled CML inputs; AC coupling required.
9 AD1/EQA1 input SMBus slave address input AD1 in SMBus mode; as EQA1 in Pin Mode it is not used and must always be tied to GND.
10 AD0/EQA0 input SMBus slave address input AD0 in SMBus mode, or EQA0 equalization level control for the A direction in Pin Mode (4-level LVCMOS).
11 INB+ input Non-inverting CML differential input to the equalizer of channel B with on-chip 50 Ω termination to VDD enabled by RXDET control logic; AC coupling required.
12 INB- input Inverting CML differential input to the equalizer of channel B with on-chip 50 Ω termination to VDD enabled by RXDET control logic; AC coupling required.
13 RES input Reserved pin; this input must be left floating.
14 SD_TH input 4-level input controlling the internal signal detect threshold, for system debug only and not controlling the high speed datapath.
15 VIN power_in In 3.3 V mode feed 3.3 V to VIN to power the internal regulator; in 2.5 V mode leave floating.
16 VDD_SEL input Controls the internal regulator: float = 2.5 V mode, tie GND = 3.3 V mode.
17 READEN/VOD_SEL input READEN: logic low starts external EEPROM load (ENSMB float) and must be tied low for AD[3:0] to be active in SMBus slave mode; VOD_SEL controls the low-frequency ratio of input to output voltage amplitude in Pin Mode.
18 DONE/RXDET bidirectional DONE output: HIGH = external EEPROM load failed or incomplete, LOW = passed; RXDET input in Pin Mode selects 50 Ω or >50 kΩ input termination (set to logic 1 for SAS/SATA to keep termination enabled).
19 OUTB- output Inverting 50 Ω driver output of channel B, compatible with AC coupled CML inputs; AC coupling required.
20 OUTB+ output Non-inverting 50 Ω driver output of channel B, compatible with AC coupled CML inputs; AC coupling required.
21 VDD power_in CML/analog power supply pin: connect to 2.5 V in 2.5 V mode (2.375 V to 2.625 V), or decouple with a cap to GND in 3.3 V mode.
22 VDD power_in CML/analog power supply pin: connect to 2.5 V in 2.5 V mode (2.375 V to 2.625 V), or decouple with a cap to GND in 3.3 V mode.
23 INA- input Inverting CML differential input to the equalizer of channel A with on-chip 50 Ω termination to VDD enabled by RXDET control logic; AC coupling required.
24 INA+ input Non-inverting CML differential input to the equalizer of channel A with on-chip 50 Ω termination to VDD enabled by RXDET control logic; AC coupling required.
25 GND power_in Die attach pad and the only device ground connection; connect to GND through multiple (minimum of 4) vias for electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24-EP(4x4)
Category Interface
Pins 25

CAD (KiCad official)

  • Symbol: DS125BR111RTWR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ds125br111rtwr-etched.step / ds125br111rtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds125br111rtwr.step / ds125br111rtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 0b7cee4cabe65671, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF