component
DS1232LPSN-2+T&R
Public Made by Adomby adom
Maxim Integrated Monitors & Reset Circuits, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDS1232LPSN-2+T&R
Maxim Integrated · Monitors & Reset Circuits · SOIC-8
DS1232LPSN-2+T&R from Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PBRST | input | Pushbutton reset input requiring an active low signal; internally pulled up to VCC with about 40k typical impedance and debounced, generating reset pulses of at least 250 ms after release. |
| 2 | TD | passive | Time delay set input: GND gives a typical 150 ms watchdog timeout, left unconnected gives 600 ms, and VCC gives 1.2 seconds. |
| 3 | TOL | input | Selects the VCC detect threshold: connected to GND sets the reset trip near 4.75 V, connected to VCC sets it near 4.5 V. |
| 4 | GND | power_in | Ground reference for all voltages; supply and I/O levels are referenced to ground. |
| 5 | RST | output | Reset output, active low, open drain; VOL is 0.4 V max at 10 mA sink, and it remains within 0.5 V of GND on power-down until VCC drops below 2.0 V. |
| 6 | RST | output | Reset output, active high, driven to within 0.5 V of VCC during power-down until VCC drops below 2.0 V; asserted for at least 250 ms on power-up and on watchdog or pushbutton reset. |
| 7 | ST | input | Strobe input for the watchdog timer; a high-to-low transition must occur before timeout, with VIH of 2.0 V min and VIL of 0.8 V max, and the watchdog cannot be disabled. |
| 8 | VCC | power_in | +5 V power supply input, monitored for out-of-tolerance conditions; recommended supply range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Maxim Integrated |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
DS1232LPSN-2+T&R - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ds1232lpsn-2-t-r-etched.step/ds1232lpsn-2-t-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds1232lpsn-2-t-r.step/ds1232lpsn-2-t-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Maxim Integrated datasheet (7 pp, sha256
159e2a53841a78da, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).