# DS1232LPS-2+T&R

**Analog Devices Inc Maxim Integrated** · Supervisor And Reset ICs · SOIC-8

DS1232LPS-2+T&R from Analog Devices Inc Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PBRST | input | Pushbutton reset input requires an active-low signal, is internally pulled up to VCC (about 40k typical), and is debounced to generate a reset of at least 250 ms. |
| 2 | TD | input | Time delay set for the watchdog: tied to GND gives about 150 ms, left unconnected gives about 600 ms, and tied to VCC gives about 1.2 s timeout. |
| 3 | TOL | input | Selects the VCC detect threshold: tied to GND sets the reset trip at 4.75 V, and tied to VCC sets it at 4.5 V. |
| 4 | GND | power_in | Ground reference for all voltages on the device. |
| 5 | RST | output | Reset output, active high, driven to the active state on VCC out-of-tolerance, watchdog timeout, or pushbutton reset, and held active for at least 250 ms. |
| 6 | RST | output | Reset output, active low, open-drain, driven to the active state on the same reset conditions and held active for at least 250 ms. |
| 7 | ST | input | Strobe input: a high-to-low transition must occur before watchdog timeout to prevent a reset, with a minimum pulse width tST of 20 ns. |
| 8 | VCC | power_in | +5 V supply input, with absolute maximum rating of -0.5 V to +7.0 V relative to ground and recommended operating range of 4.5 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 0°C to 70°C | 6 |
| ST and PBRST Input High Level | VIH | 2 |  |  | V | 0°C to 70°C | 6 |
| ST and PBRST Input Low Level | VIL | -0.3 |  | 0.8 | V | 0°C to 70°C | 6 |
| Input Leakage | IIL | -1 |  | 1 | µA | 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| Output Current @ 2.4V | IOH | -10 |  | -8 | mA | 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| Output Current @ 0.4V | IOL | 10 |  |  | mA | 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| Low Level @ RST | VOL |  |  | 0.4 | V | 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| Output Current (CMOS) | ICC1 |  |  | 50 | µA | Measured with outputs open and ST and PBRST within 0.5V of supply rails | 6 |
| Operating Current (TTL) | ICC2 |  | 200 | 500 | µA | Measured with outputs open and ST and PBRST at TTL levels | 6 |
| VCC Trip Point (TOL=GND) | VCCTP | 4.5 | 4.62 | 4.74 | V | TOL=GND; 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| VCC Trip Point (TOL=VCC) | VCCTP | 4.25 | 4.37 | 4.49 | V | TOL=VCC; 0°C to 70°C; VCC=4.5 to 5.5V | 6 |
| Voltage on VCC Pin Relative to Ground |  | -0.5 |  | 7 | V |  | 6 |
| Voltage on I/O Relative to Ground |  | -0.5 |  |  | V |  | 6 |
| Operating Temperature |  | 0 |  | 70 | °C |  | 6 |
| Storage Temperature |  | -55 |  | 125 | °C |  | 6 |
| Soldering Temperature |  |  |  | 260 | °C | for 10 seconds | 6 |
| PBRST = VIL | tPB | 20 |  |  | ms | 0°C to 70°C; VCC=5V ± 10% | 7 |
| RESET Active Time | tRST | 250 | 610 | 1000 | ms | 0°C to 70°C; VCC=5V ± 10% | 7 |
| ST Pulse Width | tST | 20 |  |  | ns | Must not exceed tTD minimum (Table 1); watchdog cannot be disabled | 7 |
| VCC Fail Detect to RST and RST | tRPD |  | 50 | 175 | µs | 0°C to 70°C; VCC=5V ± 10% | 7 |
| VCC Slew Rate 4.75V to 4.25V | tF |  |  | 300 | µs | 0°C to 70°C; VCC=5V ± 10% | 7 |
| VCC Detect to RST and RST Inactive | tRPU | 250 | 610 | 1000 | ms | tR = 5 µs; 0°C to 70°C; VCC=5V ± 10% | 7 |
| VCC Slew Rate 4.25V to 4.75V | tR | 0 |  |  | ns | 0°C to 70°C; VCC=5V ± 10% | 7 |
| PBRST Stable Low to RST and RST | tPDLY | 20 |  |  | ms | 0°C to 70°C; VCC=5V ± 10% | 7 |
| Watchdog Time-Out (TD = GND) | tTD | 62.5 | 150 | 250 | ms | TD connected to GND | 4 |
| Watchdog Time-Out (TD Float) | tTD | 250 | 600 | 1000 | ms | TD left unconnected | 4 |
| Watchdog Time-Out (TD = VCC) | tTD | 500 | 1200 | 2000 | ms | TD connected to VCC | 4 |
| Input Capacitance | CIN |  | 5 |  | pF | tA=25°C | 6 |
| Output Capacitance | COUT |  | 7 |  | pF | tA=25°C | 6 |

## CAD (KiCad official)

- Symbol: `DS1232LPS-2+T&R`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ds1232lps-2-t-r-etched.step` / `ds1232lps-2-t-r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds1232lps-2-t-r.step` / `ds1232lps-2-t-r.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices Inc Maxim Integrated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588879933321433088) (7 pp, sha256 `159e2a53841a78da`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ds1232lps-2-t-r-datasheet.pdf)