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DS110DF410SQ

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Texas Instruments Clock And Data Recovery / Retiming, WQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS110DF410SQ

Texas Instruments · Clock And Data Recovery / Retiming · WQFN-48(7x7)

DS110DF410SQ from Texas Instruments, in a WQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXP0 input Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
2 RXN0 input Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
3 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
4 RXP1 input Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
5 RXN1 input Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
6 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
7 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
8 RXP2 input Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
9 RXN2 input Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
10 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
11 RXP3 input Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
12 RXN3 input Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled.
13 LPF_REF_3 passive Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_3.
14 LPF_CP_3 bidirectional Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_3.
15 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
16 LOCK_3/ADDR_3 output 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 3; shared with the ADDR_3 SMBus address strap, which is read at power-up.
17 SDC bidirectional 3.3 V LVCMOS SMBus clock open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor.
18 SDA bidirectional 3.3 V LVCMOS SMBus data open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor.
19 REFCLK_IN input 2.5 V analog input for the 25 MHz ±100 ppm reference clock from an external oscillator; no stringent phase noise requirement.
20 EN_SMB input 2.5 V analog input selecting SMBus mode: high for slave mode, float for master mode; READ_EN must be tied low in slave mode.
21 LOCK_2/ADDR_2 output 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 2; shared with the ADDR_2 SMBus address strap, which is read at power-up.
22 GND power_in Ground reference.
23 LPF_CP_2 bidirectional Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_2.
24 LPF_REF_2 passive Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_2.
25 TXN3 output Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
26 TXP3 output Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
27 GND power_in Ground reference.
28 TXN2 output Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
29 TXP2 output Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
30 GND power_in Ground reference.
31 GND power_in Ground reference.
32 TXN1 output Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
33 TXP1 output Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
34 GND power_in Ground reference.
35 TXN0 output Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
36 TXP0 output Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled.
37 LPF_REF_1 passive Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_1.
38 LPF_CP_1 bidirectional Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_1.
39 GND power_in Ground reference.
40 LOCK_1/ADDR_1 output 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 1; shared with the ADDR_1 SMBus address strap, which is read at power-up.
41 ALL_DONE output 2.5 V LVCMOS output that goes low to indicate the SMBus master EEPROM read has completed.
42 REFCLK_OUT output 2.5 V analog output carrying a buffered replica of the reference clock input, used to daisy-chain multiple DS110DF410 devices.
43 INT output Active-low open-drain interrupt output, 3.3 V LVCMOS tolerant, signaling eye opening out of tolerance, loss of signal, or CDR unlock; requires an external 2 kΩ to 5 kΩ pull-up.
44 READ_EN input 2.5 V LVCMOS input where a high-to-low transition starts loading from the external EEPROM; must be tied low in SMBus slave mode.
45 LOCK_0/ADDR_0 output 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 0; shared with the ADDR_0 SMBus address strap, which is read at power-up.
46 VDD power_in Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V).
47 LPF_CP_0 bidirectional Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_0.
48 LPF_REF_0 passive Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_0.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: DS110DF410SQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds110df410sq-etched.step / ds110df410sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds110df410sq.step / ds110df410sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 560a5ba18d189254, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF