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DS110DF410SQ
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Texas Instruments Clock And Data Recovery / Retiming, WQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# DS110DF410SQ++**Texas Instruments** · Clock And Data Recovery / Retiming · WQFN-48(7x7)++DS110DF410SQ from Texas Instruments, in a WQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RXP0 | input | Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 2 | RXN0 | input | Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 3 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 4 | RXP1 | input | Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 5 | RXN1 | input | Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 6 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 7 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 8 | RXP2 | input | Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 9 | RXN2 | input | Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 10 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 11 | RXP3 | input | Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 12 | RXN3 | input | Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled. |+| 13 | LPF_REF_3 | passive | Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_3. |+| 14 | LPF_CP_3 | bidirectional | Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_3. |+| 15 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 16 | LOCK_3/ADDR_3 | output | 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 3; shared with the ADDR_3 SMBus address strap, which is read at power-up. |+| 17 | SDC | bidirectional | 3.3 V LVCMOS SMBus clock open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor. |+| 18 | SDA | bidirectional | 3.3 V LVCMOS SMBus data open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor. |+| 19 | REFCLK_IN | input | 2.5 V analog input for the 25 MHz ±100 ppm reference clock from an external oscillator; no stringent phase noise requirement. |+| 20 | EN_SMB | input | 2.5 V analog input selecting SMBus mode: high for slave mode, float for master mode; READ_EN must be tied low in slave mode. |+| 21 | LOCK_2/ADDR_2 | output | 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 2; shared with the ADDR_2 SMBus address strap, which is read at power-up. |+| 22 | GND | power_in | Ground reference. |+| 23 | LPF_CP_2 | bidirectional | Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_2. |+| 24 | LPF_REF_2 | passive | Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_2. |+| 25 | TXN3 | output | Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 26 | TXP3 | output | Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 27 | GND | power_in | Ground reference. |+| 28 | TXN2 | output | Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 29 | TXP2 | output | Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 30 | GND | power_in | Ground reference. |+| 31 | GND | power_in | Ground reference. |+| 32 | TXN1 | output | Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 33 | TXP1 | output | Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 34 | GND | power_in | Ground reference. |+| 35 | TXN0 | output | Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 36 | TXP0 | output | Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled. |+| 37 | LPF_REF_1 | passive | Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_1. |+| 38 | LPF_CP_1 | bidirectional | Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_1. |+| 39 | GND | power_in | Ground reference. |+| 40 | LOCK_1/ADDR_1 | output | 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 1; shared with the ADDR_1 SMBus address strap, which is read at power-up. |+| 41 | ALL_DONE | output | 2.5 V LVCMOS output that goes low to indicate the SMBus master EEPROM read has completed. |+| 42 | REFCLK_OUT | output | 2.5 V analog output carrying a buffered replica of the reference clock input, used to daisy-chain multiple DS110DF410 devices. |+| 43 | INT | output | Active-low open-drain interrupt output, 3.3 V LVCMOS tolerant, signaling eye opening out of tolerance, loss of signal, or CDR unlock; requires an external 2 kΩ to 5 kΩ pull-up. |+| 44 | READ_EN | input | 2.5 V LVCMOS input where a high-to-low transition starts loading from the external EEPROM; must be tied low in SMBus slave mode. |+| 45 | LOCK_0/ADDR_0 | output | 2.5 V LVCMOS output that goes high when CDR lock is attained on channel 0; shared with the ADDR_0 SMBus address strap, which is read at power-up. |+| 46 | VDD | power_in | Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V). |+| 47 | LPF_CP_0 | bidirectional | Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_0. |+| 48 | LPF_REF_0 | passive | Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_0. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-48(7x7) |+| Category | Clock/Timing |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DS110DF410SQ`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: WQFN-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `ds110df410sq-etched.step` / `ds110df410sq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds110df410sq.step` / `ds110df410sq.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds110df410) (64 pp, sha256 `560a5ba18d189254`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds110df410sq-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "ds110df410sq",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds110df410sq.kicad_sym",+ "ds110df410sq.kicad_mod",+ "ds110df410sq.glb",+ "ds110df410sq.step",+ "ds110df410sq.lbr",+ "docs/hero.png",+ "docs/ds110df410sq-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds110df410sq-hero.glb",+ "ds110df410sq-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS110DF410SQ",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-48(7x7)",+ "pin_count": 49,+ "category": "Clock/Timing",+ "subcategory": "Clock And Data Recovery / Retiming",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds110df410",+ "parts": {+ "symbol": "ds110df410sq.kicad_sym",+ "footprint": "ds110df410sq.kicad_mod",+ "model_3d": "ds110df410sq-hero.glb",+ "model_3d_plain": "ds110df410sq.glb",+ "model_3d_step": "ds110df410sq-etched.step",+ "model_3d_step_plain": "ds110df410sq.step",+ "lbr": "ds110df410sq.lbr"+ },+ "distributor_links": {+ "lcsc": "C2863491"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:33:19Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RXP0",+ "type": "input",+ "description": "Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "2",+ "name": "RXN0",+ "type": "input",+ "description": "Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "4",+ "name": "RXP1",+ "type": "input",+ "description": "Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "5",+ "name": "RXN1",+ "type": "input",+ "description": "Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "7",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "8",+ "name": "RXP2",+ "type": "input",+ "description": "Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "9",+ "name": "RXN2",+ "type": "input",+ "description": "Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "11",+ "name": "RXP3",+ "type": "input",+ "description": "Non-inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "12",+ "name": "RXN3",+ "type": "input",+ "description": "Inverting CML-compatible differential input to the equalizer, with nominal differential input impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "13",+ "name": "LPF_REF_3",+ "type": "passive",+ "description": "Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_3."+ },+ {+ "number": "14",+ "name": "LPF_CP_3",+ "type": "bidirectional",+ "description": "Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_3."+ },+ {+ "number": "15",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "16",+ "name": "LOCK_3/ADDR_3",+ "type": "output",+ "description": "2.5 V LVCMOS output that goes high when CDR lock is attained on channel 3; shared with the ADDR_3 SMBus address strap, which is read at power-up."+ },+ {+ "number": "17",+ "name": "SDC",+ "type": "bidirectional",+ "description": "3.3 V LVCMOS SMBus clock open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor."+ },+ {+ "number": "18",+ "name": "SDA",+ "type": "bidirectional",+ "description": "3.3 V LVCMOS SMBus data open-drain input/output; requires an external 2 kΩ to 5 kΩ pull-up resistor."+ },+ {+ "number": "19",+ "name": "REFCLK_IN",+ "type": "input",+ "description": "2.5 V analog input for the 25 MHz ±100 ppm reference clock from an external oscillator; no stringent phase noise requirement."+ },+ {+ "number": "20",+ "name": "EN_SMB",+ "type": "input",+ "description": "2.5 V analog input selecting SMBus mode: high for slave mode, float for master mode; READ_EN must be tied low in slave mode."+ },+ {+ "number": "21",+ "name": "LOCK_2/ADDR_2",+ "type": "output",+ "description": "2.5 V LVCMOS output that goes high when CDR lock is attained on channel 2; shared with the ADDR_2 SMBus address strap, which is read at power-up."+ },+ {+ "number": "22",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "23",+ "name": "LPF_CP_2",+ "type": "bidirectional",+ "description": "Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_2."+ },+ {+ "number": "24",+ "name": "LPF_REF_2",+ "type": "passive",+ "description": "Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_2."+ },+ {+ "number": "25",+ "name": "TXN3",+ "type": "output",+ "description": "Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "26",+ "name": "TXP3",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "27",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "28",+ "name": "TXN2",+ "type": "output",+ "description": "Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "29",+ "name": "TXP2",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "30",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "31",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "32",+ "name": "TXN1",+ "type": "output",+ "description": "Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "33",+ "name": "TXP1",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "34",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "35",+ "name": "TXN0",+ "type": "output",+ "description": "Inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "36",+ "name": "TXP0",+ "type": "output",+ "description": "Non-inverting CML-compatible differential output from the driver, with nominal differential output impedance of 100 Ω; must be AC coupled."+ },+ {+ "number": "37",+ "name": "LPF_REF_1",+ "type": "passive",+ "description": "Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_1."+ },+ {+ "number": "38",+ "name": "LPF_CP_1",+ "type": "bidirectional",+ "description": "Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_1."+ },+ {+ "number": "39",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "40",+ "name": "LOCK_1/ADDR_1",+ "type": "output",+ "description": "2.5 V LVCMOS output that goes high when CDR lock is attained on channel 1; shared with the ADDR_1 SMBus address strap, which is read at power-up."+ },+ {+ "number": "41",+ "name": "ALL_DONE",+ "type": "output",+ "description": "2.5 V LVCMOS output that goes low to indicate the SMBus master EEPROM read has completed."+ },+ {+ "number": "42",+ "name": "REFCLK_OUT",+ "type": "output",+ "description": "2.5 V analog output carrying a buffered replica of the reference clock input, used to daisy-chain multiple DS110DF410 devices."+ },+ {+ "number": "43",+ "name": "INT",+ "type": "output",+ "description": "Active-low open-drain interrupt output, 3.3 V LVCMOS tolerant, signaling eye opening out of tolerance, loss of signal, or CDR unlock; requires an external 2 kΩ to 5 kΩ pull-up."+ },+ {+ "number": "44",+ "name": "READ_EN",+ "type": "input",+ "description": "2.5 V LVCMOS input where a high-to-low transition starts loading from the external EEPROM; must be tied low in SMBus slave mode."+ },+ {+ "number": "45",+ "name": "LOCK_0/ADDR_0",+ "type": "output",+ "description": "2.5 V LVCMOS output that goes high when CDR lock is attained on channel 0; shared with the ADDR_0 SMBus address strap, which is read at power-up."+ },+ {+ "number": "46",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply pin; VDD = 2.5 V ±5% (2.375 V to 2.625 V)."+ },+ {+ "number": "47",+ "name": "LPF_CP_0",+ "type": "bidirectional",+ "description": "Analog loop filter connection; a 22 nF ±10% capacitor is placed between this pin and LPF_REF_0."+ },+ {+ "number": "48",+ "name": "LPF_REF_0",+ "type": "passive",+ "description": "Loop filter reference connection; a 22 nF ±10% capacitor is placed between this pin and LPF_CP_0."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed center pad (DAP, described as power ground that must connect to the board ground plane w; LPF_REF_n pins have no I/O type in the pin table (the table only says to place a 22 nF capacitor bet; LOCK_n/ADDR_n pins are shared: the datasheet lists them as LOCK outputs but also as ADDR strap input",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.1163,+ "at": "2026-10-07T23:32:59"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds110df410",+ "pages": 64,+ "sha256": "560a5ba18d189254",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds110df410sq.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds110df410sq-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "979498ca89bf17b611564260b2f1e7b9d21aace08501b06d9cf9d2c04b930bb4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}