DS110DF111SQE from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LPF_REF_A	passive	Loop filter connection; place a 22 nF capacitor in series between LPF_CP_A and LPF_REF_A.
2	LPF_CP_A	passive	Loop filter connection; place a 22 nF capacitor in series between LPF_CP_A and LPF_REF_A.
3	ENSMB	input	4-level SMBus enable: HIGH selects register access/SMBus slave mode, FLOAT selects SMBus master mode (EEPROM read), LOW selects external pin control mode.
4	SDA/DEMA	bidirectional	SMBus data input/open-drain output that requires an external pull-up and is 3.3 V LVCMOS tolerant; in pin control mode (ENSMB = LOW) it sets the CHA output de-emphasis level.
5	SCL/DEMB	bidirectional	SMBus clock input in slave mode (open-drain output in master mode), 3.3 V LVCMOS tolerant; in pin control mode (ENSMB = LOW) it sets the CHB output de-emphasis level.
6	TX_DIS/LBK	input	4-level input: in SMBus control mode, HIGH disables the OUTB transmitter and LOW enables OUTA/OUTB; in pin control mode it is LBK, which selects the INA/INB-to-OUTA/OUTB routing.
7	OUTA+	output	Non-inverting CML-compatible differential output for channel A; outputs require AC coupling.
8	OUTA-	output	Inverting CML-compatible differential output for channel A; outputs require AC coupling.
9	VODA/READEN#	input	In SMBus master mode READEN# pulled low starts the EEPROM configuration read (must be tied LOW in slave mode); in pin control mode it is a 4-level input that sets the CHA output launch amplitude.
10	ADDR1/VODB/DONE#	bidirectional	Strap input read at power-up to set SMBus address bit 1; in SMBus master mode DONE# is driven low when the EEPROM read completes, and in pin control mode it is a 4-level input that sets the CHB output launch amplitude.
11	INB+	input	Non-inverting CML-compatible differential input for channel B with an on-chip 100 Ohm termination; inputs require AC coupling (100 nF recommended).
12	INB-	input	Inverting CML-compatible differential input for channel B with an on-chip 100 Ohm termination; inputs require AC coupling (100 nF recommended).
13	LOS/INT#	output	Open-drain output driven LOW when a valid signal is present on CH A and released on loss of signal; can be redefined as INT# driven LOW when the EOM check falls below the HEO/VEO threshold, and requires an external 3.3 V pull-up.
14	REFCLK_IN	input	LVCMOS reference clock input for a 25 MHz ±100 ppm clock from an external oscillator.
15	VIN	power_in	Regulator input with integrated supply mode control: 3.3 V ±10% in 3.3 V mode, or 2.5 V ±5% in 2.5 V mode.
16	ADDR0/LOCK	bidirectional	Strap input read at power-up to set SMBus address bit 0; also the LOCK output, driven HIGH when CDR lock is attained on the corresponding channel.
17	LPF_CP_B	passive	Loop filter connection; place a 22 nF capacitor in series between LPF_CP_B and LPF_REF_B.
18	LPF_REF_B	passive	Loop filter connection; place a 22 nF capacitor in series between LPF_CP_B and LPF_REF_B.
19	OUTB-	output	Inverting CML-compatible differential output for channel B; outputs require AC coupling.
20	OUTB+	output	Non-inverting CML-compatible differential output for channel B; outputs require AC coupling.
21	VDD	power_in	2.5 V ±5% supply; in 3.3 V mode this pin is the internal regulator output at 2.5 V ±5%.
22	VDD	power_in	2.5 V ±5% supply; in 3.3 V mode this pin is the internal regulator output at 2.5 V ±5%.
23	INA-	input	Inverting CML-compatible differential input for channel A with an on-chip 100 Ohm termination; inputs require AC coupling (100 nF recommended).
24	INA+	input	Non-inverting CML-compatible differential input for channel A with an on-chip 100 Ohm termination; inputs require AC coupling (100 nF recommended).
25	DAP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-24-EP(4x4)
Category	Communication Interface Chip/UART/485/232
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD)	VDD	-0.5		2.75	V		5
Supply Voltage (VIN)	VIN	-0.5		4	V		5
LVCMOS Input/Output Voltage		-0.5		4	V		5
4-Level Input Voltage		-0.5		2.75	V	2.5 V mode	5
4-Level Input Voltage		-0.5		4	V	3.3 V mode	5
SMBus Input/Output Voltage		-0.5		4	V		5
CML Input Voltage		-0.5			V	max printed as VDD + 0.5 V (not numeric)	5
CML Input Current		-30		30	mA		5
Storage Temperature	Tstg	-40		125	°C		5
Supply Voltage		2.375	2.5	2.625	V	2.5 V Mode	5
Supply Voltage		3	3.3	3.6	V	3.3 V Mode	5
Ambient Temperature		-40	25	85	°C		5
SMBus (SDA, SCL) Voltage		3	3.3	3.6	V	SDA, SCL	5
Input baud rate	R_baud	8.5		11.3	Gbps	Full Rate: DS110DF111	6
SMBus Clock Rate (slave mode)	FSDC	100		400	kHz	Slave Mode Clock Rate	6
SMBus Clock Rate (master mode)	FSDC	280	400	520	kHz	Master Mode Clock Rate	6
Whole Device Supply Current	IDD			170	mA	11.3 Gbps : DS110DF111	6
Whole Device Supply Current	IDD			150	mA	11.3 Gbps : DS110DF111, DFE Disabled	6
Whole Device Maximum Transient Supply Current	IDD		235	300	mA	Default Settings: CHA and CHB, valid input signal detected, CHA and CHB acquiring LOCK	6
Supply Noise Tolerance	NTps			100	mVp-p	50 Hz to 100 Hz	6
Supply Noise Tolerance	NTps			40	mVp-p	100 Hz to 10 MHz	6
Supply Noise Tolerance	NTps			10	mVp-p	10 MHz to 5.0 GHz	6
High level input voltage (LVCMOS)	VIH	1.7			V	2.5 V or 3.3 V Supply Modes; max printed as VIN (not numeric)	6
Low level input voltage (LVCMOS)	VIL			0.7	V	2.5 V or 3.3 V Supply Modes	6
High level output voltage (LVCMOS)	VOH	2			V	IOH = -3 mA; max printed as VIN (not numeric)	6
Low level output voltage (LVCMOS)	VOL			0.4	V	IOL = 3 mA	6
Input leakage current (LVCMOS)	IIN	-15		15	µA	VINPUT = GND or VIN	6
Input leakage current (4-level inputs)	IIN-R	-160		80	µA	VINPUT = GND or VIN	6
Low level output voltage (open drain LOS/INT#)	VOL			0.4	V	IOL = 3 mA	6
Input Return-Loss	RLRX-IN			-19	dB	SDD11 10 MHz	6
Input Return-Loss	RLRX-IN			-14	dB	SDD11 2.0 GHz	6
Input Return-Loss	RLRX-IN			-8	dB	SDD11 6.0 - 11.1 GHz	6
Source Transmit Signal Level	VRX-	600		1600	mVp-p	Launch	6
Output differential voltage	T_VDIFF0	400	550	675	mVp-p	Default setting, PRBS31	6
Output differential voltage	T_VDIFF7	1000		1250	mVp-p	Maximum setting, PRBS31; Requires SMBus Control	6
De-emphasis Level	VOD_DE	-12			dB	Maximum setting, VOD and DE; Requires SMBus Control	6
Output Rise/Fall Time 20%-80%	TR/TF			36	ps	Input: 10.3125Gbps, 64T pattern; Full Slew Rate	6
Output Rise/Fall Time 20%-80% (limited slew rate)	TRS/TFS			50	ps	Input: 10.3125 Gbps, 8T Pattern; Limited Slew Rate (Reg 0x18)	6
Output differential mode return loss	TSDD22			-19	dB	SDD22 10 MHz - 2 GHz	7
Output differential mode return loss	TSDD22			-15	dB	SDD22 5.5GHz	7
Output differential mode return loss	TSDD22			-11	dB	SDD22 11.1GHz	7
Propagation Delay (retimed data)	TPD			350	ps	Retimed Data 10.3125 Gbps	7
Propagation Delay (raw data)	TPD-RAW			200	ps	Raw Data	7
Total Jitter (1E-12)	TTJ			7.5	ps	PRBS7, 10.3125 Gbps	7
Random Jitter	TRJ			0.33	ps (RMS)	PRBS7, 10.3125 Gbps	7
Deterministic Jitter	TDJ			3.6	ps	PRBS7, 10.3125 Gbps	7
Total jitter tolerance	JTOL	0.7			UI	Jitter per SFF-8431 Appendix D.11; combination of Dj, Pj, and Rj	7
CDR Lock Time	TLOCK1	10		30	ms	Standards Based	7
High level input voltage (SDA/SCL)	VIH	2.1		3.6	V	Data, Clock Input High Voltage (SDA / SCL)	7
Low level input voltage (SDA/SCL)	VIL			0.8	V	Data, Clock Input Low Voltage (SDA / SCL)	7
Output Low Voltage (SDA/SCL)	VOL	0		0.36	V	SDA or SCL, IOL = 1.25 mA	7
Signal Detect ON Threshold Level	SDH		20		mVp-p	Default level to assert; Signal Detect, 10.3125 Gbps	6
Signal Detect OFF Threshold Level	SDL		15		mVp-p	Default level to de-assert; Signal Detect, 10.3125 Gbps	6
DC Input differential Resistance	R_Rd		100		Ω		6
Junction-to-ambient thermal resistance	θJA		35		°C/W		5
Junction-to-case (top) thermal resistance	RθJC(top)		34		°C/W		5
Junction-to-board thermal resistance	RθJB		13.4		°C/W		5
Junction-to-top characterization parameter	ψJT		0.3		°C/W		5
Junction-to-board characterization parameter	ψJB		13.4		°C/W		5
Junction-to-case (bottom) thermal resistance	RθJC(bot)		3.3		°C/W		5

CAD (KiCad official)

Symbol: DS110DF111SQE
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: ds110df111sqe-etched.step / ds110df111sqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds110df111sqe.step / ds110df111sqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (55 pp, sha256 aca1fe01fdbc6bf7, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS110DF111SQE

Verified DS110DF111SQE

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3D Model

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Datasheet

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