component
DS10CP154ATSQX
Public Made by Adomby adom
Texas Instruments Signal Switches / Encoders & Decoders / Multiplexers, QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DS10CP154ATSQX
Texas Instruments · Signal Switches / Encoders & Decoders / Multiplexers · QFN-40-EP(6x6)
DS10CP154ATSQX from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN0+ | input | Non-inverting high-speed LVDS input for channel IN0, internally terminated with 100 Ω between IN0+ and IN0-. |
| 2 | IN0- | input | Inverting high-speed LVDS input for channel IN0, internally terminated with 100 Ω between IN0+ and IN0-, with differential input voltage VID specified at 0 to 1.0 V. |
| 3 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 4 | IN1+ | input | Non-inverting high-speed LVDS input for channel IN1, internally terminated with 100 Ω between IN1+ and IN1-. |
| 5 | IN1- | input | Inverting high-speed LVDS input for channel IN1, internally terminated with 100 Ω between IN1+ and IN1-. |
| 6 | IN2+ | input | Non-inverting high-speed LVDS input for channel IN2, internally terminated with 100 Ω between IN2+ and IN2-. |
| 7 | IN2- | input | Inverting high-speed LVDS input for channel IN2, internally terminated with 100 Ω between IN2+ and IN2-. |
| 8 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 9 | IN3+ | input | Non-inverting high-speed LVDS input for channel IN3, internally terminated with 100 Ω between IN3+ and IN3-. |
| 10 | IN3- | input | Inverting high-speed LVDS input for channel IN3, internally terminated with 100 Ω between IN3+ and IN3-. |
| 11 | NC | unconnected | No-connect pin; may be left floating. |
| 12 | NC | unconnected | No-connect pin; may be left floating. |
| 13 | S30 | input | LVCMOS input selecting the OUT3 source in Pin Mode (EN_smb = 0); in SMBus mode it is non-functional and should be tied to logic 0 or 1. |
| 14 | S31 | input | LVCMOS input selecting the OUT3 source in Pin Mode (EN_smb = 0, with S30); in SMBus mode it is non-functional and should be tied to logic 0 or 1. |
| 15 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 16 | GND | power_in | Power ground pin. |
| 17 | EN_smb | input | SMBus mode enable: logic 1 selects SMBus mode and logic 0 selects Pin Mode; the pin has an internal 20 kΩ pull-down and all SMBus registers reset when it is toggled. |
| 18 | NC | unconnected | No-connect pin; may be left floating. |
| 19 | NC | unconnected | No-connect pin; may be left floating. |
| 20 | NC | unconnected | No-connect pin; may be left floating. |
| 21 | OUT3- | output | Inverting LVDS output for channel OUT3, with 100 Ω termination between OUT3+ and OUT3- and LVDS output levels. |
| 22 | OUT3+ | output | Non-inverting LVDS output for channel OUT3, with 100 Ω termination between OUT3+ and OUT3- and LVDS output levels. |
| 23 | OUT2- | output | Inverting LVDS output for channel OUT2, with 100 Ω termination between OUT2+ and OUT2- and LVDS output levels. |
| 24 | OUT2+ | output | Non-inverting LVDS output for channel OUT2, with 100 Ω termination between OUT2+ and OUT2- and LVDS output levels. |
| 25 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 26 | OUT1- | output | Inverting LVDS output for channel OUT1, with 100 Ω termination between OUT1+ and OUT1- and LVDS output levels. |
| 27 | OUT1+ | output | Non-inverting LVDS output for channel OUT1, with 100 Ω termination between OUT1+ and OUT1- and LVDS output levels. |
| 28 | OUT0- | output | Inverting LVDS output for channel OUT0, with 100 Ω termination between OUT0+ and OUT0- and LVDS output levels. |
| 29 | OUT0+ | output | Non-inverting LVDS output for channel OUT0, with 100 Ω termination between OUT0+ and OUT0- and LVDS output levels. |
| 30 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 31 | NC | unconnected | No-connect pin; may be left floating. |
| 32 | S21/ADDR3 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT2 (with S20); in SMBus mode it is the user-set slave address input ADDR3, tied to GND for 0 or VCC for 1. |
| 33 | S20/ADDR2 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT2 (with S21); in SMBus mode it is the user-set slave address input ADDR2, tied to GND for 0 or VCC for 1. |
| 34 | S11/ADDR1 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT1 (with S10); in SMBus mode it is the user-set slave address input ADDR1, tied to GND for 0 or VCC for 1. |
| 35 | S10/ADDR0 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT1 (with S11); in SMBus mode it is the user-set slave address input ADDR0, tied to GND for 0 or VCC for 1. |
| 36 | S01/SDA | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT0 (with S00); in SMBus mode it is the SMBus serial data I/O pin, with VOL limited to 0.4 V at 4 mA. |
| 37 | S00/SCL | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT0 (with S01); in SMBus mode it is the SMBus clock input. |
| 38 | PWDN | input | LVCMOS power-down pin: logic 0 powers the device down in Pin Mode (SMBus remains accessible when EN_smb = 1) and logic 1 powers it up. |
| 39 | NC | unconnected | No-connect pin; may be left floating. |
| 40 | NC | unconnected | No-connect pin; may be left floating. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-40-EP(6x6) |
| Category | Logic ICs |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
DS10CP154ATSQX - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
ds10cp154atsqx-etched.step/ds10cp154atsqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds10cp154atsqx.step/ds10cp154atsqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
2152387064801720, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DS10CP154ATSQX
**Texas Instruments** · Signal Switches / Encoders & Decoders / Multiplexers · QFN-40-EP(6x6)
DS10CP154ATSQX from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN0+ | input | Non-inverting high-speed LVDS input for channel IN0, internally terminated with 100 Ω between IN0+ and IN0-. |
| 2 | IN0- | input | Inverting high-speed LVDS input for channel IN0, internally terminated with 100 Ω between IN0+ and IN0-, with differential input voltage VID specified at 0 to 1.0 V. |
| 3 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 4 | IN1+ | input | Non-inverting high-speed LVDS input for channel IN1, internally terminated with 100 Ω between IN1+ and IN1-. |
| 5 | IN1- | input | Inverting high-speed LVDS input for channel IN1, internally terminated with 100 Ω between IN1+ and IN1-. |
| 6 | IN2+ | input | Non-inverting high-speed LVDS input for channel IN2, internally terminated with 100 Ω between IN2+ and IN2-. |
| 7 | IN2- | input | Inverting high-speed LVDS input for channel IN2, internally terminated with 100 Ω between IN2+ and IN2-. |
| 8 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 9 | IN3+ | input | Non-inverting high-speed LVDS input for channel IN3, internally terminated with 100 Ω between IN3+ and IN3-. |
| 10 | IN3- | input | Inverting high-speed LVDS input for channel IN3, internally terminated with 100 Ω between IN3+ and IN3-. |
| 11 | NC | unconnected | No-connect pin; may be left floating. |
| 12 | NC | unconnected | No-connect pin; may be left floating. |
| 13 | S30 | input | LVCMOS input selecting the OUT3 source in Pin Mode (EN_smb = 0); in SMBus mode it is non-functional and should be tied to logic 0 or 1. |
| 14 | S31 | input | LVCMOS input selecting the OUT3 source in Pin Mode (EN_smb = 0, with S30); in SMBus mode it is non-functional and should be tied to logic 0 or 1. |
| 15 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 16 | GND | power_in | Power ground pin. |
| 17 | EN_smb | input | SMBus mode enable: logic 1 selects SMBus mode and logic 0 selects Pin Mode; the pin has an internal 20 kΩ pull-down and all SMBus registers reset when it is toggled. |
| 18 | NC | unconnected | No-connect pin; may be left floating. |
| 19 | NC | unconnected | No-connect pin; may be left floating. |
| 20 | NC | unconnected | No-connect pin; may be left floating. |
| 21 | OUT3- | output | Inverting LVDS output for channel OUT3, with 100 Ω termination between OUT3+ and OUT3- and LVDS output levels. |
| 22 | OUT3+ | output | Non-inverting LVDS output for channel OUT3, with 100 Ω termination between OUT3+ and OUT3- and LVDS output levels. |
| 23 | OUT2- | output | Inverting LVDS output for channel OUT2, with 100 Ω termination between OUT2+ and OUT2- and LVDS output levels. |
| 24 | OUT2+ | output | Non-inverting LVDS output for channel OUT2, with 100 Ω termination between OUT2+ and OUT2- and LVDS output levels. |
| 25 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 26 | OUT1- | output | Inverting LVDS output for channel OUT1, with 100 Ω termination between OUT1+ and OUT1- and LVDS output levels. |
| 27 | OUT1+ | output | Non-inverting LVDS output for channel OUT1, with 100 Ω termination between OUT1+ and OUT1- and LVDS output levels. |
| 28 | OUT0- | output | Inverting LVDS output for channel OUT0, with 100 Ω termination between OUT0+ and OUT0- and LVDS output levels. |
| 29 | OUT0+ | output | Non-inverting LVDS output for channel OUT0, with 100 Ω termination between OUT0+ and OUT0- and LVDS output levels. |
| 30 | VDD | power_in | Power supply pin; VCC is specified at 3.0 V to 3.6 V (3.3 V typical). |
| 31 | NC | unconnected | No-connect pin; may be left floating. |
| 32 | S21/ADDR3 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT2 (with S20); in SMBus mode it is the user-set slave address input ADDR3, tied to GND for 0 or VCC for 1. |
| 33 | S20/ADDR2 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT2 (with S21); in SMBus mode it is the user-set slave address input ADDR2, tied to GND for 0 or VCC for 1. |
| 34 | S11/ADDR1 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT1 (with S10); in SMBus mode it is the user-set slave address input ADDR1, tied to GND for 0 or VCC for 1. |
| 35 | S10/ADDR0 | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT1 (with S11); in SMBus mode it is the user-set slave address input ADDR0, tied to GND for 0 or VCC for 1. |
| 36 | S01/SDA | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT0 (with S00); in SMBus mode it is the SMBus serial data I/O pin, with VOL limited to 0.4 V at 4 mA. |
| 37 | S00/SCL | bidirectional | In Pin Mode (EN_smb = 0) it is the LVCMOS select input for OUT0 (with S01); in SMBus mode it is the SMBus clock input. |
| 38 | PWDN | input | LVCMOS power-down pin: logic 0 powers the device down in Pin Mode (SMBus remains accessible when EN_smb = 1) and logic 1 powers it up. |
| 39 | NC | unconnected | No-connect pin; may be left floating. |
| 40 | NC | unconnected | No-connect pin; may be left floating. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-40-EP(6x6) |
| Category | Logic ICs |
| Pins | 41 |
## CAD (KiCad official)
- Symbol: `DS10CP154ATSQX`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `ds10cp154atsqx-etched.step` / `ds10cp154atsqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds10cp154atsqx.step` / `ds10cp154atsqx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds10cp154a) (21 pp, sha256 `2152387064801720`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ds10cp154atsqx-datasheet.pdf)