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DS10BR254TSQX

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Texas Instruments LVDS ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS10BR254TSQX

Texas Instruments · LVDS ICs · WQFN-40-EP(6x6)

DS10BR254TSQX from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin; may be left floating.
2 NC unconnected No connect pin; may be left floating.
3 VDD power_in Power supply pin; the device is specified for a supply voltage (VCC) of 3.0 V to 3.6 V.
4 IN1+ input Non-inverting high-speed LVDS input of channel 1, internally terminated with 100 Ω between IN1+ and IN1-.
5 IN1- input Inverting high-speed LVDS input of channel 1, internally terminated with 100 Ω between IN1+ and IN1-.
6 IN2+ input Non-inverting high-speed LVDS input of channel 2, internally terminated with 100 Ω between IN2+ and IN2-.
7 IN2- input Inverting high-speed LVDS input of channel 2, internally terminated with 100 Ω between IN2+ and IN2-.
8 VDD power_in Power supply pin; the device is specified for a supply voltage (VCC) of 3.0 V to 3.6 V.
9 NC unconnected No connect pin; may be left floating.
10 NC unconnected No connect pin; may be left floating.
11 NC unconnected No connect pin; may be left floating.
12 NC unconnected No connect pin; may be left floating.
13 NC unconnected No connect pin; may be left floating.
14 SEL_in input LVCMOS input that selects the active LVDS input: logic 0 selects IN1 and logic 1 selects IN2.
15 VDD power_in Power supply pin; the device is specified for a supply voltage (VCC) of 3.0 V to 3.6 V.
16 GND power_in Power ground pin.
17 NC unconnected No connect pin; may be left floating.
18 NC unconnected No connect pin; may be left floating.
19 NC unconnected No connect pin; may be left floating.
20 NC unconnected No connect pin; may be left floating.
21 OUT3- output Inverting high-speed LVDS output of channel 3; LVDS-compliant differential output with 100 Ω termination between OUT3+ and OUT3-.
22 OUT3+ output Non-inverting high-speed LVDS output of channel 3; LVDS-compliant differential output with 100 Ω termination between OUT3+ and OUT3-.
23 OUT2- output Inverting high-speed LVDS output of channel 2; LVDS-compliant differential output with 100 Ω termination between OUT2+ and OUT2-.
24 OUT2+ output Non-inverting high-speed LVDS output of channel 2; LVDS-compliant differential output with 100 Ω termination between OUT2+ and OUT2-.
25 VDD power_in Power supply pin; the device is specified for a supply voltage (VCC) of 3.0 V to 3.6 V.
26 OUT1- output Inverting high-speed LVDS output of channel 1; LVDS-compliant differential output with 100 Ω termination between OUT1+ and OUT1-.
27 OUT1+ output Non-inverting high-speed LVDS output of channel 1; LVDS-compliant differential output with 100 Ω termination between OUT1+ and OUT1-.
28 OUT0- output Inverting high-speed LVDS output of channel 0; LVDS-compliant differential output with 100 Ω termination between OUT0+ and OUT0-.
29 OUT0+ output Non-inverting high-speed LVDS output of channel 0; LVDS-compliant differential output with 100 Ω termination between OUT0+ and OUT0-.
30 VDD power_in Power supply pin; the device is specified for a supply voltage (VCC) of 3.0 V to 3.6 V.
31 NC unconnected No connect pin; may be left floating.
32 PWDN3 input Channel 3 output power-down input; when set low, output OUT3 is in power-down mode.
33 PWDN2 input Channel 2 output power-down input; when set low, output OUT2 is in power-down mode.
34 PWDN1 input Channel 1 output power-down input; when set low, output OUT1 is in power-down mode.
35 PWDN0 input Channel 0 output power-down input; when set low, output OUT0 is in power-down mode.
36 LOS2 output Loss-of-signal open-drain output that reports an open-input fault at IN2; an external pull-up resistor is required.
37 LOS1 output Loss-of-signal open-drain output that reports an open-input fault at IN1; an external pull-up resistor is required.
38 PWDN input Device power-down input; when set low, the whole device is in power-down mode.
39 NC unconnected No connect pin; may be left floating.
40 NC unconnected No connect pin; may be left floating.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Interface
Pins 41

CAD (KiCad official)

  • Symbol: DS10BR254TSQX
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds10br254tsqx-etched.step / ds10br254tsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds10br254tsqx.step / ds10br254tsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 65cecd34213f0351, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF