component

DS10BR254TSQ

Public Made by Adom

by adom

Texas Instruments LVDS ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ds10br254tsqfactory-2.0.0extractor-text

Verified DS10BR254TSQ

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DS10BR254TSQ · WQFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 19-page datasheet
  • •distributor (warn): no ['mouser'] number
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-wmjtcoux/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ds10br254tsq.kicad_sym✓ ds10br254tsq.kicad_mod✓ ds10br254tsq.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ds10br254tsq / README.md
History Download
Ray Publish 0.1.0 f90fdd5

DS10BR254TSQ

Texas Instruments · LVDS ICs · WQFN-40-EP(6x6)

DS10BR254TSQ from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No-connect pin that may be left floating.
2 NC unconnected No-connect pin that may be left floating.
3 VDD power_in Power supply pin.
4 IN1+ input Non-inverting high speed LVDS input pin of channel 1.
5 IN1- input Inverting high speed LVDS input pin of channel 1.
6 IN2+ input Non-inverting high speed LVDS input pin of channel 2.
7 IN2- input Inverting high speed LVDS input pin of channel 2.
8 VDD power_in Power supply pin.
9 NC unconnected No-connect pin that may be left floating.
10 NC unconnected No-connect pin that may be left floating.
11 NC unconnected No-connect pin that may be left floating.
12 NC unconnected No-connect pin that may be left floating.
13 NC unconnected No-connect pin that may be left floating.
14 SEL_in input LVCMOS input that selects which LVDS input is active (0 selects IN1, 1 selects IN2).
15 VDD power_in Power supply pin.
16 GND power_in Ground pin.
17 NC unconnected No-connect pin that may be left floating.
18 NC unconnected No-connect pin that may be left floating.
19 NC unconnected No-connect pin that may be left floating.
20 NC unconnected No-connect pin that may be left floating.
21 OUT3- output Inverting high speed LVDS output pin of channel 3.
22 OUT3+ output Non-inverting high speed LVDS output pin of channel 3.
23 OUT2- output Inverting high speed LVDS output pin of channel 2.
24 OUT2+ output Non-inverting high speed LVDS output pin of channel 2.
25 VDD power_in Power supply pin.
26 OUT1- output Inverting high speed LVDS output pin of channel 1.
27 OUT1+ output Non-inverting high speed LVDS output pin of channel 1.
28 OUT0- output Inverting high speed LVDS output pin of channel 0.
29 OUT0+ output Non-inverting high speed LVDS output pin of channel 0.
30 VDD power_in Power supply pin.
31 NC unconnected No-connect pin that may be left floating.
32 PWDN3 input LVCMOS channel output power down pin; when set to L, output OUT3 is in power down mode.
33 PWDN2 input LVCMOS channel output power down pin; when set to L, output OUT2 is in power down mode.
34 PWDN1 input LVCMOS channel output power down pin; when set to L, output OUT1 is in power down mode.
35 PWDN0 input LVCMOS channel output power down pin; when set to L, output OUT0 is in power down mode.
36 LOS2 output LVCMOS open-drain loss of signal output that reports an open input fault on IN2; external pull-up resistor required.
37 LOS1 output LVCMOS open-drain loss of signal output that reports an open input fault on IN1; external pull-up resistor required.
38 PWDN input LVCMOS device power down pin; when set to L, the device is in power down mode.
39 NC unconnected No-connect pin that may be left floating.
40 NC unconnected No-connect pin that may be left floating.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Communication Interface Chip/UART/485/232
Pins 41

CAD (KiCad official)

  • Symbol: DS10BR254TSQ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: ds10br254tsq-etched.step / ds10br254tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds10br254tsq.step / ds10br254tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 ec58d031595a80cc, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF