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DS08MB200TSQX

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Texas Instruments LVDS ICs, WQFN-48-EP(7x7.3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DS08MB200TSQX

Texas Instruments · LVDS ICs · WQFN-48-EP(7x7.3)

DS08MB200TSQX from Texas Instruments, in a WQFN-48-EP(7x7.3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N/C unconnected No connect pin, listed as N/C in the pin description table.
2 GND power_in Ground reference for LVDS and CMOS circuitry.
3 GND power_in Ground reference for LVDS and CMOS circuitry.
4 ENL_1 input LVTTL output enable control for the Line-side channel 1 output driver; each Line-side output driver has its own enable pin.
5 N/C unconnected No connect pin, listed as N/C in the pin description table.
6 VDD power_in Power supply pin, VDD = 3.3V ±0.3V (recommended operating supply 3.0V to 3.6V).
7 LO_1+ output Line-side channel 1 non-inverting LVDS differential output, LVDS compatible.
8 LO_1- output Line-side channel 1 inverting LVDS differential output, LVDS compatible.
9 LI_1+ input Line-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible, with on-chip 100 Ω input termination.
10 LI_1- input Line-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible, with on-chip 100 Ω input termination.
11 MUX_S1 input Mux select control input for channel 1, selects whether Switch-side A or B input is passed to the Line-side (LVTTL).
12 VDD power_in Power supply pin, VDD = 3.3V ±0.3V.
13 ENA_1 input LVTTL output enable control for the Switch A-side channel 1 output driver; each A-side driver has its own enable pin.
14 ENB_1 input LVTTL output enable control for the Switch B-side channel 1 output driver; each B-side driver has its own enable pin.
15 SOA_1+ output Switch A-side channel 1 non-inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
16 SOA_1- output Switch A-side channel 1 inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
17 SOB_1+ output Switch B-side channel 1 non-inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
18 SOB_1- output Switch B-side channel 1 inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
19 SIA_1+ input Switch A-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
20 SIA_1- input Switch A-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
21 SIB_1+ input Switch B-side channel 1 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
22 SIB_1- input Switch B-side channel 1 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
23 N/C unconnected No connect pin, listed as N/C in the pin description table.
24 N/C unconnected No connect pin, listed as N/C in the pin description table.
25 N/C unconnected No connect pin, listed as N/C in the pin description table.
26 N/C unconnected No connect pin, listed as N/C in the pin description table.
27 SIB_0- input Switch B-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
28 SIB_0+ input Switch B-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
29 SIA_0- input Switch A-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
30 SIA_0+ input Switch A-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible.
31 SOB_0- output Switch B-side channel 0 inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
32 SOB_0+ output Switch B-side channel 0 non-inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
33 SOA_0- output Switch A-side channel 0 inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
34 SOA_0+ output Switch A-side channel 0 non-inverting LVDS differential output, LVDS compatible (point-to-point use only, not multidrop BLVDS).
35 ENB_0 input LVTTL output enable control for the Switch B-side channel 0 output driver; each B-side driver has its own enable pin.
36 ENA_0 input LVTTL output enable control for the Switch A-side channel 0 output driver; each A-side driver has its own enable pin.
37 VDD power_in Power supply pin, VDD = 3.3V ±0.3V.
38 MUX_S0 input Mux select control input for channel 0, selects whether Switch-side A or B input is passed to the Line-side (LVTTL).
39 LI_0- input Line-side channel 0 inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible, with on-chip 100 Ω input termination.
40 LI_0+ input Line-side channel 0 non-inverting differential input, LVDS, Bus LVDS, CML, or LVPECL compatible, with on-chip 100 Ω input termination.
41 LO_0- output Line-side channel 0 inverting LVDS differential output, LVDS compatible.
42 LO_0+ output Line-side channel 0 non-inverting LVDS differential output, LVDS compatible.
43 VDD power_in Power supply pin, VDD = 3.3V ±0.3V.
44 N/C unconnected No connect pin, listed as N/C in the pin description table.
45 ENL_0 input LVTTL output enable control for the Line-side channel 0 output driver; each Line-side output driver has its own enable pin.
46 GND power_in Ground reference for LVDS and CMOS circuitry.
47 GND power_in Ground reference for LVDS and CMOS circuitry.
48 VDD power_in Power supply pin, VDD = 3.3V ±0.3V.
49 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7.3)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS08MB200TSQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7.3) (KiCad packages3D, STEP)
  • 3D model files: ds08mb200tsqx-etched.step / ds08mb200tsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds08mb200tsqx.step / ds08mb200tsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 d7c79c9325619d86, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF