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DRV8955PRGER

Public Made by Adom

by adom

Texas Instruments Gate Drive ICs, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8955PRGER

Texas Instruments · Gate Drive ICs · VQFN-24(4x4)

DRV8955PRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Power supply input connected to the supply voltage (4.5 V to 48 V recommended) and bypassed to PGND with a 0.01 µF ceramic capacitor per pin plus a bulk capacitor rated for VM.
2 PGND power_in Power ground, connected to system ground.
3 OUT1 output Half-bridge 1 output.
4 OUT2 output Half-bridge 2 output.
5 OUT4 output Half-bridge 4 output.
6 OUT3 output Half-bridge 3 output.
7 PGND power_in Power ground, connected to system ground.
8 VM power_in Power supply input connected to the supply voltage (4.5 V to 48 V recommended) and bypassed to PGND with a 0.01 µF ceramic capacitor per pin plus a bulk capacitor rated for VM.
9 GND power_in Device ground, connected to system ground.
10 DVDD power_out Logic supply voltage (nominal 5 V, up to 2 mA load), bypassed to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V.
11 nFAULT output Fault indication pulled logic low on a fault condition; open-drain output requiring an external pull-up resistor.
12 VREF34/EN4 input Reference voltage input setting the current level of half-bridges 3 and 4 when MODE is 0, 1 or Hi-Z; with a 330k resistor from MODE to ground, logic high enables OUT4.
13 VREF12/EN3 input Reference voltage input setting the current level of half-bridges 1 and 2 when MODE is 0, 1 or Hi-Z; with a 330k resistor from MODE to ground, logic high enables OUT3.
14 TOFF/EN2 input Sets the off time during current chopping when MODE is 0, 1 or Hi-Z; with a 330k resistor from MODE to ground, logic high enables OUT2.
15 RSVD/EN1 passive Leave unconnected when MODE is 0, 1 or Hi-Z; with a 330k resistor from MODE to ground, logic high enables OUT1.
16 MODE input Four-level input selecting half-bridge paralleling or independent Hi-Z operation: 0 gives four independent solenoid loads, 1 pairs half-bridges for two loads, open parallels all for one load, 330k to ground enables independent Hi-Z control.
17 IN4 input PWM input logically controlling the state of half-bridge 4, with internal pull-down.
18 IN3 input PWM input logically controlling the state of half-bridge 3, with internal pull-down.
19 IN2 input PWM input logically controlling the state of half-bridge 2, with internal pull-down.
20 IN1 input PWM input logically controlling the state of half-bridge 1, with internal pull-down.
21 nSLEEP input Sleep mode input: logic high enables the device, logic low enters low-power sleep mode, with internal pull-down; do not connect to DVDD.
22 CPL passive Charge pump switching node; connect a VM-rated X7R 0.022 µF ceramic capacitor between CPH and CPL.
23 CPH passive Charge pump switching node; connect a VM-rated X7R 0.022 µF ceramic capacitor between CPH and CPL.
24 VCP output Charge pump output, connected to VM through an X7R 0.22 µF 16 V ceramic capacitor.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Power Supply Chip
Pins 25

CAD (KiCad official)

  • Symbol: DRV8955PRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8955prger-etched.step / drv8955prger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8955prger.step / drv8955prger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 fda4d2456aba29b4, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF