# DRV8932PRGER

**Texas Instruments** · Gate Drive ICs · VQFN-24-EP(4x4)

DRV8932PRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VM | power_in | Power supply pin connected to the supply voltage, bypassed to PGND with two 0.01 µF ceramic capacitors (one per pin) and a bulk capacitor rated for VM. |
| 2 | PGND | power_in | Common power ground for all four half-bridges, connected to the system ground. |
| 3 | OUT1 | output | Output of half-bridge 1. |
| 4 | OUT2 | output | Output of half-bridge 2. |
| 5 | OUT4 | output | Output of half-bridge 4. |
| 6 | OUT3 | output | Output of half-bridge 3. |
| 7 | PGND | power_in | Common power ground for all four half-bridges, connected to the system ground. |
| 8 | VM | power_in | Power supply pin connected to the supply voltage, bypassed to PGND with two 0.01 µF ceramic capacitors (one per pin) and a bulk capacitor rated for VM. |
| 9 | GND | power_in | Device ground, connected to the system ground. |
| 10 | DVDD | power_out | Logic supply voltage from the internal regulator; bypass to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 11 | nFAULT | output | Fault indication output that is pulled low during a fault; it is open-drain and requires an external pull-up resistor. |
| 12 | VREF34 | input | Reference voltage input that sets the current level of half-bridges 3 and 4. |
| 13 | VREF12 | input | Reference voltage input that sets the current level of half-bridges 1 and 2. |
| 14 | TOFF | input | Four-level pin that sets the off-time during current chopping. |
| 15 | NC | unconnected | No internal connection. |
| 16 | NC | unconnected | No internal connection. |
| 17 | IN4 | input | PWM input that controls the state of half-bridge 4; internal pull-down. |
| 18 | IN3 | input | PWM input that controls the state of half-bridge 3; internal pull-down. |
| 19 | IN2 | input | PWM input that controls the state of half-bridge 2; internal pull-down. |
| 20 | IN1 | input | PWM input that controls the state of half-bridge 1; internal pull-down. |
| 21 | nSLEEP | input | Sleep mode input: logic high enables the device, logic low puts it into low-power sleep mode; internal pull-down. |
| 22 | CPL | passive | Charge pump negative switch node; connect a X7R 0.022 µF ceramic capacitor rated VM between CPH and CPL. |
| 23 | CPH | passive | Charge pump switch node; connect a X7R 0.022 µF ceramic capacitor rated VM between CPH and CPL. |
| 24 | VCP | output | Charge pump output; connect a X7R 0.22 µF 16 V ceramic capacitor between VCP and VM. |
| 25 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VM | -0.3 |  | 35 | V |  | 6 |
| Charge pump voltage | VCP, CPH | -0.3 |  |  | V |  | 6 |
| Charge pump negative switch pin voltage | CPL | -0.3 |  |  | V |  | 6 |
| nSLEEP pin voltage | nSLEEP | -0.3 |  |  | V |  | 6 |
| Internal regulator voltage | DVDD | -0.3 |  | 5.75 | V |  | 6 |
| Control pin voltage | IN1, IN2, IN3, IN4, nFAULT, TOFF | -0.3 |  | 5.75 | V |  | 6 |
| Open-drain output current | nFAULT | 0 |  | 10 | mA |  | 6 |
| Reference input pin voltage | VREF12, VREF34 | -0.3 |  | 5.75 | V |  | 6 |
| Continuous phase node voltage | OUT1, OUT2, OUT3, OUT4 | -1 |  |  | V |  | 6 |
| Transient 100 ns phase node voltage | OUT1, OUT2, OUT3, OUT4 | -3 |  |  | V | 100 ns transient | 6 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 6 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 6 |
| VM supply voltage range for normal DC operation | VVM | 4.5 |  | 33 | V |  | 7 |
| Logic-level input voltage | VI | 0 |  | 5.5 | V |  | 7 |
| Reference RMS voltage range | VREF | 0.05 |  | 3.3 | V |  | 7 |
| Applied PWM frequency | fPWM | 0 |  | 100 | kHz | IN1, IN2, IN3, IN4 | 7 |
| Peak output current | IFS | 0 |  | 1.5 | A |  | 7 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 7 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 7 |
| VM operating supply current | IVM |  | 5 | 6.5 | mA | nSLEEP = 1, no load | 8 |
| VM sleep-mode supply current | IVMQ |  | 2 | 4 | μA | nSLEEP = 0 | 8 |
| Sleep time | tSLEEP |  |  | 120 | μs | nSLEEP = 0 to sleep mode | 8 |
| nSLEEP reset pulse | tRESET | 20 |  | 40 | μs | nSLEEP low to clear fault | 8 |
| Wake-up time | tWAKE |  | 0.8 | 1.2 | ms | nSLEEP = 1 to output switching | 8 |
| Turn-on time | tON |  | 0.8 | 1.2 | ms | VM > UVLO to output switching | 8 |
| Internal regulator voltage | VDVDD | 4.5 | 5 | 5.5 | V | No external load, 6V < VVM < 33V | 8 |
| Internal regulator voltage at low VM | VDVDD | 4.2 |  | 4.35 | V | VVM = 4.5V | 8 |
| Input logic low voltage | VIL | 0 |  | 0.6 | V |  | 8 |
| Input logic high voltage | VIH | 1.5 |  | 5.5 | V |  | 8 |
| Input logic low current | IIL | -1 |  | 1 | μA | VIN = 0V | 8 |
| Input logic high current | IIH |  |  | 100 | μA | VIN = 5V | 8 |
| Four-level input low voltage (TOFF) | VI1 | 0 |  | 0.6 | V | Connected to GND | 8 |
| Four-level input 330 kΩ voltage (TOFF) | VI2 | 1 | 1.25 | 1.4 | V | 330kΩ ± 5% to GND | 8 |
| Four-level input high-impedance voltage (TOFF) | VI3 | 1.8 | 2 | 2.2 | V | High impedance (>500kΩ to GND) | 8 |
| Four-level input logic high voltage (TOFF) | VI4 | 2.7 |  | 5.5 | V | Connected to DVDD | 8 |
| nFAULT output logic low voltage | VOL |  |  | 0.5 | V | IO = 5mA | 8 |
| nFAULT output logic high leakage current | IOH | -1 |  | 1 | μA |  | 8 |
| High-side FET on-resistance | RDS(ONH) |  | 450 | 550 | mΩ | TJ = 25°C, IO = -1A | 8 |
| High-side FET on-resistance | RDS(ONH) |  | 700 | 850 | mΩ | TJ = 125°C, IO = -1A | 8 |
| High-side FET on-resistance | RDS(ONH) |  | 780 | 950 | mΩ | TJ = 150°C, IO = -1A | 8 |
| Low-side FET on-resistance | RDS(ONL) |  | 450 | 550 | mΩ | TJ = 25°C, IO = 1A | 8 |
| Low-side FET on-resistance | RDS(ONL) |  | 700 | 850 | mΩ | TJ = 125°C, IO = 1A | 8 |
| Low-side FET on-resistance | RDS(ONL) |  | 780 | 950 | mΩ | TJ = 150°C, IO = 1A | 8 |
| Transconductance gain (current sense) | KV | 2.09 | 2.2 | 2.31 | V/A | VREF = 3.3V | 8 |
| Current trip accuracy | ΔITRIP | -15 |  | 15 | % | IO = 1.5A, 10% to 20% current setting | 9 |
| Current trip accuracy | ΔITRIP | -10 |  | 10 | % | IO = 1.5A, 20% to 67% current setting | 9 |
| Current trip accuracy | ΔITRIP | -5 |  | 5 | % | IO = 1.5A, 68% to 100% current setting | 9 |
| VM undervoltage lockout falling threshold | VUVLO | 4.1 | 4.25 | 4.35 | V | VM falling, UVLO falling | 9 |
| VM undervoltage lockout rising threshold | VUVLO | 4.2 | 4.35 | 4.45 | V | VM rising, UVLO rising | 9 |
| Thermal shutdown temperature | TOTSD | 150 | 165 | 180 | °C | Core temperature TJ | 9 |
| Overcurrent protection current | IOCP |  | 2.5 |  | A | Current through any FET | 9 |
| Overcurrent deglitch time | tOCP |  | 1.8 |  | μs |  | 9 |
| Thermal shutdown hysteresis | THYS_OTSD |  | 20 |  | °C | Core temperature TJ | 9 |
| Junction-to-ambient thermal resistance (VQFN, RGE) | RθJA |  | 43 |  | °C/W |  | 7 |
| Junction-to-case (top) thermal resistance (VQFN, RGE) | RθJC(top) |  | 35 |  | °C/W |  | 7 |
| Junction-to-board thermal resistance (VQFN, RGE) | RθJB |  | 19.9 |  | °C/W |  | 7 |
| Junction-to-top characterization parameter (VQFN, RGE) | ψJT |  | 1 |  | °C/W |  | 7 |
| Junction-to-board characterization parameter (VQFN, RGE) | ψJB |  | 19.8 |  | °C/W |  | 7 |
| Junction-to-case (bottom) thermal resistance (VQFN, RGE) | RθJC(bot) |  | 6.7 |  | °C/W |  | 7 |

## CAD (KiCad official)

- Symbol: `DRV8932PRGER`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `drv8932prger-etched.step` / `drv8932prger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8932prger.step` / `drv8932prger.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8932) (42 pp, sha256 `0c8af1781c344c22`, retrieved 2026-10-30, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8932prger-datasheet.pdf)