component
DRV8876NPWPR
Public Made by Adomby adom
Texas Instruments Brushed DC Motor Drivers, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+54@@ -0,0 +1,54 @@+# DRV8876NPWPR++**Texas Instruments** · Brushed DC Motor Drivers · HTSSOP-16-EP++DRV8876NPWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | EN/IN1 | input | H bridge control input with internal pull-down; accepts PWM or static signals for motor control in PH/EN and PWM modes. |+| 2 | PH/IN2 | input | H bridge control input with internal pull-down; accepts PWM or static signals for speed and direction control. |+| 3 | nSLEEP | input | Sleep mode control input with internal pull-down; logic high enables device, logic low enters sleep mode with quiescent current <1µA. |+| 4 | nFAULT | tri_state | Open-drain fault indicator output; driven low during UVLO, CPUV, OCP, or TSD conditions; requires external pull-up resistor. |+| 5 | RSVD1 | input | Reserved input pin; connect to voltage greater than 1V; recommended to connect to system logic power supply rail or nSLEEP. |+| 6 | RSVD2 | output | Reserved output pin; connect to system ground as recommended in typical application circuits. |+| 7 | IMODE | input | Over-current protection mode selection 4-level input; connect to GND for automatic retry mode, leave floating for output latch mode. |+| 8 | OUT1 | output | H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode. |+| 9 | PGND | power_in | Device power ground return; connect to system ground plane to complete current path from motor outputs. |+| 10 | OUT2 | output | H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode. |+| 11 | VM | power_in | Main motor supply power input, 4.5V to 37V; bypass to GND with 0.1µF and connect large bulk capacitor per section 9.1. |+| 12 | VCP | power_out | Charge pump regulated output, nominally 5V above VM; connect 100nF X5R or X7R 16V ceramic capacitor between VCP and VM. |+| 13 | CPH | passive | Charge pump high-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins. |+| 14 | CPL | passive | Charge pump low-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins. |+| 15 | GND | power_in | Device signal ground reference; connect to system ground plane for proper circuit operation. |+| 16 | PMODE | input | H bridge control mode selection 3-level input; logic low=PH/EN mode, high=PWM mode, high-Z=independent half-bridge mode. |+| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-16-EP |+| Category | Motor Driver ICs |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `DRV8876NPWPR`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `drv8876npwpr-etched.step` / `drv8876npwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8876npwpr.step` / `drv8876npwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8876n) (34 pp, sha256 `7ca82ef869aa7e02`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8876npwpr-datasheet.pdf)
page.jsonadded+199@@ -0,0 +1,199 @@+{+ "slug": "drv8876npwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushed DC Motor Drivers, HTSSOP-16-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8876npwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8876npwpr.kicad_sym",+ "drv8876npwpr.kicad_mod",+ "drv8876npwpr.glb",+ "drv8876npwpr.step",+ "drv8876npwpr.lbr",+ "docs/hero.png",+ "docs/drv8876npwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8876NPWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-16-EP",+ "pin_count": 17,+ "category": "Motor Driver ICs",+ "subcategory": "Brushed DC Motor Drivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8876n",+ "parts": {+ "symbol": "drv8876npwpr.kicad_sym",+ "footprint": "drv8876npwpr.kicad_mod",+ "model_3d": "drv8876npwpr-etched.glb",+ "model_3d_plain": "drv8876npwpr.glb",+ "model_3d_step": "drv8876npwpr-etched.step",+ "model_3d_step_plain": "drv8876npwpr.step",+ "lbr": "drv8876npwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C1849483"+ },+ "pins": [+ {+ "number": "1",+ "name": "EN/IN1",+ "type": "input",+ "description": "H bridge control input with internal pull-down; accepts PWM or static signals for motor control in PH/EN and PWM modes."+ },+ {+ "number": "2",+ "name": "PH/IN2",+ "type": "input",+ "description": "H bridge control input with internal pull-down; accepts PWM or static signals for speed and direction control."+ },+ {+ "number": "3",+ "name": "nSLEEP",+ "type": "input",+ "description": "Sleep mode control input with internal pull-down; logic high enables device, logic low enters sleep mode with quiescent current <1µA."+ },+ {+ "number": "4",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Open-drain fault indicator output; driven low during UVLO, CPUV, OCP, or TSD conditions; requires external pull-up resistor."+ },+ {+ "number": "5",+ "name": "RSVD1",+ "type": "input",+ "description": "Reserved input pin; connect to voltage greater than 1V; recommended to connect to system logic power supply rail or nSLEEP."+ },+ {+ "number": "6",+ "name": "RSVD2",+ "type": "output",+ "description": "Reserved output pin; connect to system ground as recommended in typical application circuits."+ },+ {+ "number": "7",+ "name": "IMODE",+ "type": "input",+ "description": "Over-current protection mode selection 4-level input; connect to GND for automatic retry mode, leave floating for output latch mode."+ },+ {+ "number": "8",+ "name": "OUT1",+ "type": "output",+ "description": "H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode."+ },+ {+ "number": "9",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground return; connect to system ground plane to complete current path from motor outputs."+ },+ {+ "number": "10",+ "name": "OUT2",+ "type": "output",+ "description": "H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode."+ },+ {+ "number": "11",+ "name": "VM",+ "type": "power_in",+ "description": "Main motor supply power input, 4.5V to 37V; bypass to GND with 0.1µF and connect large bulk capacitor per section 9.1."+ },+ {+ "number": "12",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump regulated output, nominally 5V above VM; connect 100nF X5R or X7R 16V ceramic capacitor between VCP and VM."+ },+ {+ "number": "13",+ "name": "CPH",+ "type": "passive",+ "description": "Charge pump high-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins."+ },+ {+ "number": "14",+ "name": "CPL",+ "type": "passive",+ "description": "Charge pump low-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins."+ },+ {+ "number": "15",+ "name": "GND",+ "type": "power_in",+ "description": "Device signal ground reference; connect to system ground plane for proper circuit operation."+ },+ {+ "number": "16",+ "name": "PMODE",+ "type": "input",+ "description": "H bridge control mode selection 3-level input; logic low=PH/EN mode, high=PWM mode, high-Z=independent half-bridge mode."+ },+ {+ "number": "17",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: RSVD1 and RSVD2 are reserved pins with unclear functional purpose in the datasheet. RSVD1 is marked ",+ "exposed pad 17 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 34,+ "cost_usd": 0.3636,+ "at": "2026-09-23T18:18:12"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8876n",+ "pages": 34,+ "sha256": "7ca82ef869aa7e02",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}