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Contents

README

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DRV8876NPWPR

Texas Instruments · Brushed DC Motor Drivers · HTSSOP-16-EP

DRV8876NPWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN/IN1 input H bridge control input with internal pull-down; accepts PWM or static signals for motor control in PH/EN and PWM modes.
2 PH/IN2 input H bridge control input with internal pull-down; accepts PWM or static signals for speed and direction control.
3 nSLEEP input Sleep mode control input with internal pull-down; logic high enables device, logic low enters sleep mode with quiescent current <1µA.
4 nFAULT tri_state Open-drain fault indicator output; driven low during UVLO, CPUV, OCP, or TSD conditions; requires external pull-up resistor.
5 RSVD1 input Reserved input pin; connect to voltage greater than 1V; recommended to connect to system logic power supply rail or nSLEEP.
6 RSVD2 output Reserved output pin; connect to system ground as recommended in typical application circuits.
7 IMODE input Over-current protection mode selection 4-level input; connect to GND for automatic retry mode, leave floating for output latch mode.
8 OUT1 output H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode.
9 PGND power_in Device power ground return; connect to system ground plane to complete current path from motor outputs.
10 OUT2 output H bridge driver output for motor drive; connect to motor or external load, supports 3.5A peak output current with integral body diode.
11 VM power_in Main motor supply power input, 4.5V to 37V; bypass to GND with 0.1µF and connect large bulk capacitor per section 9.1.
12 VCP power_out Charge pump regulated output, nominally 5V above VM; connect 100nF X5R or X7R 16V ceramic capacitor between VCP and VM.
13 CPH passive Charge pump high-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins.
14 CPL passive Charge pump low-side switching node; connect 22nF X5R or X7R ceramic capacitor rated for VM between CPH and CPL pins.
15 GND power_in Device signal ground reference; connect to system ground plane for proper circuit operation.
16 PMODE input H bridge control mode selection 3-level input; logic low=PH/EN mode, high=PWM mode, high-Z=independent half-bridge mode.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Motor Driver ICs
Pins 17

CAD (KiCad official)

  • Symbol: DRV8876NPWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: drv8876npwpr-etched.step / drv8876npwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8876npwpr.step / drv8876npwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 7ca82ef869aa7e02, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF